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xfree86: drivers: chips: copy over xf86-video-chips tree

Browse Source 
Since this driver doesn't receive much functional changes, except fixups
for server ABI changes, it's a good candidate to move it back into the
main Xserver tree.

As the first step to move back this driver into the Xserver tree,
copy over the source from last release tag. Skipped files we don't need
here (eg. gitlab pipeline, automake files, ...)

repo: git@github.com:X11Libre/xf86-video-chips.git
git tag: xlibre-xf86-video-chips-1.5.0.1

Signed-off-by: Enrico Weigelt, metux IT consult <info@metux.net>
This commit is contained in:
Enrico Weigelt, metux IT consult
2025-07-21 16:20:01 +02:00
committed by Enrico Weigelt
parent 6ecbce5112
commit 9b82d32978
24 changed files with 15129 additions and 0 deletions
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153
hw/xfree86/drivers/video/chips/COPYING Normal file
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Copyright 1996, 1997, 1998 by David Bateman <dbateman@ee.uts.edu.au>
Modified 1997, 1998 by Nozomi Ytow
Permission to use, copy, modify, distribute, and sell this software and its
documentation for any purpose is hereby granted without fee, provided that
the above copyright notice appear in all copies and that both that
copyright notice and this permission notice appear in supporting
documentation, and that the name of the authors not be used in
advertising or publicity pertaining to distribution of the software without
specific, written prior permission. The authors makes no representations
about the suitability of this software for any purpose. It is provided
"as is" without express or implied warranty.
THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
PERFORMANCE OF THIS SOFTWARE.
Copyright 1997
Digital Equipment Corporation. All rights reserved.
This software is furnished under license and may be used and copied only in
accordance with the following terms and conditions. Subject to these
conditions, you may download, copy, install, use, modify and distribute
this software in source and/or binary form. No title or ownership is
transferred hereby.
1) Any source code used, modified or distributed must reproduce and retain
this copyright notice and list of conditions as they appear in the
source file.
2) No right is granted to use any trade name, trademark, or logo of Digital
Equipment Corporation. Neither the "Digital Equipment Corporation" name
nor any trademark or logo of Digital Equipment Corporation may be used
to endorse or promote products derived from this software without the
prior written permission of Digital Equipment Corporation.
3) This software is provided "AS-IS" and any express or implied warranties,
including but not limited to, any implied warranties of merchantability,
fitness for a particular purpose, or non-infringement are disclaimed. In
no event shall DIGITAL be liable for any damages whatsoever, and in
particular, DIGITAL shall not be liable for special, indirect,
consequential, or incidental damages or damages for lost profits, loss
of revenue or loss of use, whether such damages arise in contract,
negligence, tort, under statute, in equity, at law or otherwise, even if
advised of the possibility of such damage.
Copyright 1994 The XFree86 Project
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
DAVID WEXELBLAT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
Copyright 1993 by Jon Block <block@frc.com>
Modified by Mike Hollick <hollick@graphics.cis.upenn.edu>
Modified 1994 by Régis Cridlig <cridlig@dmi.ens.fr>
Major Contributors to XFree86 3.2
Modified 1995/6 by Nozomi Ytow
Modified 1996 by Egbert Eich <eich@xfree86.org>
Modified 1996 by David Bateman <dbateman@club-internet.fr>
Modified 1996 by Xavier Ducoin <xavier@rd.lectra.fr>
Contributors to XFree86 3.2
Modified 1995/6 by Ken Raeburn <raeburn@raeburn.org>
Modified 1996 by Shigehiro Nomura <nomura@sm.sony.co.jp>
Modified 1996 by Marc de Courville <marc@courville.org>
Modified 1996 by Adam Sulmicki <adam@cfar.umd.edu>
Modified 1996 by Jens Maurer <jmaurer@cck.uni-kl.de>
Large parts rewritten for XFree86 4.0
Modified 1998 by David Bateman <dbateman@club-internet.fr>
Modified 1998 by Egbert Eich <eich@xfree86.org>
Modified 1998 by Nozomi Ytow
Permission to use, copy, modify, distribute, and sell this software and its
documentation for any purpose is hereby granted without fee, provided that
the above copyright notice appear in all copies and that both that
copyright notice and this permission notice appear in supporting
documentation, and that the name of the authors not be used in
advertising or publicity pertaining to distribution of the software without
specific, written prior permission. The authors makes no representations
about the suitability of this software for any purpose. It is provided
"as is" without express or implied warranty.
THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
PERFORMANCE OF THIS SOFTWARE.
Copyright 2007 George Sapountzis
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
(c) Copyright 1993,1994 by David Wexelblat <dwex@xfree86.org>
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
DAVID WEXELBLAT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
Except as contained in this notice, the name of David Wexelblat shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from David Wexelblat.

1180
hw/xfree86/drivers/video/chips/README Normal file
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.\" shorthand for double quote that works everywhere.
.ds q \N'34'
.TH CHIPS __drivermansuffix__ 2011-03-29 __vendorversion__
.SH NAME
chips \- Chips and Technologies video driver for Xorg
.SH SYNOPSIS
.nf
.B "Section \*qDevice\*q"
.BI " Identifier \*q" devname \*q
.B " Driver \*qchips\*q"
\ \ ...
.B EndSection
.fi
.SH DESCRIPTION
.B chips
is an Xorg driver for Chips and Technologies video processors.
The majority of the Chips and Technologies chipsets are supported by this driver.
In general the limitation on the capabilities of this driver are determined by
the chipset on which it is run.
Where possible, this driver provides full acceleration and
supports the following depths: 1, 4, 8, 15, 16, 24,
and on the latest chipsets, an 8+16 overlay mode.
All visual types are supported for depth 1, 4 and 8,
and both TrueColor and DirectColor visuals are supported where possible.
Multi-head configurations are supported on PCI or AGP buses.
.SH SUPPORTED HARDWARE
The
.B chips
driver supports video processors on most of the bus types currently available.
The chipsets supported fall into one of three architectural classes: a
.B basic
architecture, the
.B WinGine
architecture, and the newer
.B HiQV
architecture.
.SS Basic Architecture
The supported chipsets are
.BR ct65520 ", " ct65525 ", " ct65530 ", "
.BR ct65535 ", " ct65540 ", " ct65545 ", "
.B ct65546
and
.BR ct65548 .
.PP
Color depths 1, 4, and 8 are supported on all chipsets,
while depths 15, 16, and 24 are supported only on the
.BR 65540 ", " 65545 ", " 65546
and
.B 65548
chipsets.
The driver is accelerated when used with the
.BR 65545 ", " 65546
or
.B 65548
chipsets, however the DirectColor visual is not available.
.SS Wingine Architecture
The supported chipsets are
.B ct64200
and
.BR ct64300.
.PP
Color depths 1, 4, and 8 are supported on both chipsets,
while depths 15, 16, and 24 are supported only on the
.B 64300
chipsets.
The driver is accelerated when used with the
.B 64300
chipsets, however the DirectColor visual is not available.
.SS HiQV Architecture
The supported chipsets are
.BR ct65550 ", " ct65554 ", " ct65555 ", " ct68554 ", " ct69000
and
.BR ct69030 .
.PP
Color depths 1, 4, 8, 15, 16, 24 and 8+16 are supported on all chipsets.
The DirectColor visual is supported on all color depths except the 8+16
overlay mode.
Full acceleration is supplied for all chipsets.
.SH CONFIGURATION DETAILS
Please refer to
.BR xorg.conf (__filemansuffix__)
for general configuration details.
This section only covers configuration details specific to this driver.
.PP
The driver auto-detects the chipset type, but the following
.B ChipSet
names may optionally be specified in the config file
.B \*qDevice\*q
section, and will override the auto-detection:
.PP
.RS 4
"ct65520", "ct65525", "ct65530", "ct65535", "ct65540", "ct65545", "ct65546",
"ct65548", "ct65550", "ct65554", "ct65555", "ct68554", "ct69000", "ct69030",
"ct64200", "ct64300".
.RE
.PP
The driver will auto-detect the amount of video memory present for all chipsets,
but it may be overridden with the
.B VideoRam
entry in the config file
.B \*qDevice\*q
section.
.PP
The following driver
.B Options
are supported, on one or more of the supported chipsets:
.TP
.BI "Option \*qNoAccel\*q \*q" boolean \*q
Disable or enable acceleration.
Default: acceleration is enabled.
.TP
.BI "Option \*qNoLinear\*q \*q" boolean \*q
Disables linear addressing in cases where it is enabled by default.
Default: off
.TP
.BI "Option \*qLinear\*q \*q" boolean \*q
Enables linear addressing in cases where it is disabled by default.
Default: off
.TP
.BI "Option \*qHWCursor\*q \*q" boolean \*q
Enable or disable the HW cursor.
Default: on.
.TP
.BI "Option \*qSWCursor\*q \*q" boolean \*q
Enable or disable the SW cursor.
Default: off.
.TP
.BI "Option \*qSTN\*q \*q" boolean \*q
Force detection of STN screen type.
Default: off.
.TP
.BI "Option \*qUseModeline\*q \*q" boolean \*q
Reprogram flat panel timings with values from the modeline.
Default: off
.TP
.BI "Option \*qFixPanelSize\*q \*q" boolean \*q
Reprogram flat panel size with values from the modeline.
Default: off
.TP
.BI "Option \*qNoStretch\*q \*q" boolean \*q
This option disables the stretching on a mode on a flat panel to fill the
screen.
Default: off
.TP
.BI "Option \*qLcdCenter\*q \*q" boolean \*q
Center the mode displayed on the flat panel on the screen.
Default: off
.TP
.BI "Option \*qHWclocks\*q \*q" boolean \*q
Force the use of fixed hardware clocks on chips that support both fixed
and programmable clocks.
Default: off
.TP
.BI "Option \*qUseVclk1\*q \*q" boolean \*q
Use the Vclk1 programmable clock on
.B HiQV
chipsets instead of Vclk2.
Default: off
.TP
.BI "Option \*qFPClock8\*q \*q" float \*q
.TP
.BI "Option \*qFPClock16\*q \*q" float \*q
.TP
.BI "Option \*qFPClock24\*q \*q" float \*q
.TP
.BI "Option \*qFPClock32\*q \*q" float \*q
Force the use of a particular video clock speed for use with the
flat panel at a specified depth
.TP
.BI "Option \*qMMIO\*q \*q" boolean \*q
Force the use of memory mapped IO for acceleration registers.
Default: off
.TP
.BI "Option \*qFullMMIO\*q \*q" boolean \*q
Force the use of memory mapped IO where it can be used.
Default: off
.TP
.BI "Option \*qSuspendHack\*q \*q" boolean \*q
Force driver to leave centering and stretching registers alone.
This can fix some laptop suspend/resume problems.
Default: off
.TP
.BI "Option \*qColorKey\*q \*q" integer \*q
Set the colormap index used for the transparency key for the depth 8 plane
when operating in 8+16 overlay mode.
The value must be in the range 2\-255.
Default: 255.
.TP
.BI "Option \*qVideoKey\*q \*q" integer \*q
This sets the default pixel value for the YUV video overlay key.
Default: undefined.
.TP
.BI "Option \*qShadowFB\*q \*q" boolean \*q
Enable or disable use of the shadow framebuffer layer.
Default: off.
.TP
.BI "Option \*qSyncOnGreen\*q \*q" boolean \*q
Enable or disable combining the sync signals with the green signal.
Default: off.
.TP
.BI "Option \*qShowCache\*q \*q" boolean \*q
Enable or disable viewing offscreen memory.
Used for debugging only.
Default: off.
.TP
.BI "Option \*q18bitBus\*q \*q" boolean \*q
Force the driver to assume that the flat panel has an 18bit data bus.
Default: off.
.TP
.BI "Option \*qCrt2Memory\*q \*q" integer \*q
In a dual-head mode (69030 only) this option selects the amount of memory
to set aside for the second head.
If not specified, half the memory is used.
Default: off.
.TP
.BI "Option \*qDualRefresh\*q \*q" integer \*q
The 69030 supports independent refresh rates on its two display channels.
This mode of operations uses additional memory bandwidth and thus limits
the maximum colour depth and refresh rate that can be achieved, and so is
off by default.
Using this option forces the use of an independent refresh
rate on the two screens.
Default: off.
.TP
.BI "Option \*qFpMode\*q \*q" boolean \*q
The driver probes the chip to find out if a flat panel (LCD) is connected
and active.
If this is true it limits the possible screen size to the maximum
resolution of the panel.
The chips is initialized by the BIOS which may
set the chip to 'dual' mode even if no panel is connected.
In this case the available resolution on the CRT is limited to the panel size
the BIOS has set.
To tell the driver that no panel is connected despite
of what the BIOS is saying set this option to off.
Don't set it to off if a panel is connected.
Default: value probed by BIOS.
.SH "SEE ALSO"
.BR Xorg (__appmansuffix__),
.BR xorg.conf (__filemansuffix__),
.BR Xserver (__appmansuffix__),
.BR X (__miscmansuffix__)
.PP
You are also recommended to read the README file that comes with the driver
source, which discusses the
.B chips
driver in more detail.
.SH AUTHORS
Authors include: Jon Block, Mike Hollick, Regis Cridlig, Nozomi Ytow,
Egbert Eich, David Bateman and Xavier Ducoin

104
hw/xfree86/drivers/video/chips/src/compat-api.h Normal file
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/*
* Copyright 2012 Red Hat, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Author: Dave Airlie <airlied@redhat.com>
*/
/* this file provides API compat between server post 1.13 and pre it,
it should be reused inside as many drivers as possible */
#ifndef COMPAT_API_H
#define COMPAT_API_H
#ifndef GLYPH_HAS_GLYPH_PICTURE_ACCESSOR
#define GetGlyphPicture(g, s) GlyphPicture((g))[(s)->myNum]
#define SetGlyphPicture(g, s, p) GlyphPicture((g))[(s)->myNum] = p
#endif
#ifndef XF86_HAS_SCRN_CONV
#define xf86ScreenToScrn(s) xf86Screens[(s)->myNum]
#define xf86ScrnToScreen(s) screenInfo.screens[(s)->scrnIndex]
#endif
#ifndef XF86_SCRN_INTERFACE
#define SCRN_ARG_TYPE int
#define SCRN_INFO_PTR(arg1) ScrnInfoPtr pScrn = xf86Screens[(arg1)]
#define SCREEN_ARG_TYPE int
#define SCREEN_PTR(arg1) ScreenPtr pScreen = screenInfo.screens[(arg1)]
#define SCREEN_INIT_ARGS_DECL int i, ScreenPtr pScreen, int argc, char **argv
#define BLOCKHANDLER_ARGS_DECL int arg, pointer blockData, pointer pTimeout, pointer pReadmask
#define BLOCKHANDLER_ARGS arg, blockData, pTimeout, pReadmask
#define CLOSE_SCREEN_ARGS_DECL int scrnIndex, ScreenPtr pScreen
#define CLOSE_SCREEN_ARGS scrnIndex, pScreen
#define ADJUST_FRAME_ARGS_DECL int arg, int x, int y, int flags
#define ADJUST_FRAME_ARGS(arg, x, y) (arg)->scrnIndex, x, y, 0
#define SWITCH_MODE_ARGS_DECL int arg, DisplayModePtr mode, int flags
#define SWITCH_MODE_ARGS(arg, m) (arg)->scrnIndex, m, 0
#define FREE_SCREEN_ARGS_DECL int arg, int flags
#define VT_FUNC_ARGS_DECL int arg, int flags
#define VT_FUNC_ARGS pScrn->scrnIndex, 0
#define XF86_SCRN_ARG(x) ((x)->scrnIndex)
#else
#define SCRN_ARG_TYPE ScrnInfoPtr
#define SCRN_INFO_PTR(arg1) ScrnInfoPtr pScrn = (arg1)
#define SCREEN_ARG_TYPE ScreenPtr
#define SCREEN_PTR(arg1) ScreenPtr pScreen = (arg1)
#define SCREEN_INIT_ARGS_DECL ScreenPtr pScreen, int argc, char **argv
#if ABI_VIDEODRV_VERSION >= SET_ABI_VERSION(23, 0)
#define BLOCKHANDLER_ARGS_DECL ScreenPtr arg, pointer pTimeout
#define BLOCKHANDLER_ARGS arg, pTimeout
#else
#define BLOCKHANDLER_ARGS_DECL ScreenPtr arg, pointer pTimeout, pointer pReadmask
#define BLOCKHANDLER_ARGS arg, pTimeout, pReadmask
#endif
#define CLOSE_SCREEN_ARGS_DECL ScreenPtr pScreen
#define CLOSE_SCREEN_ARGS pScreen
#define ADJUST_FRAME_ARGS_DECL ScrnInfoPtr arg, int x, int y
#define ADJUST_FRAME_ARGS(arg, x, y) arg, x, y
#define SWITCH_MODE_ARGS_DECL ScrnInfoPtr arg, DisplayModePtr mode
#define SWITCH_MODE_ARGS(arg, m) arg, m
#define FREE_SCREEN_ARGS_DECL ScrnInfoPtr arg
#define VT_FUNC_ARGS_DECL ScrnInfoPtr arg
#define VT_FUNC_ARGS pScrn
#define XF86_SCRN_ARG(x) (x)
#endif
#endif

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hw/xfree86/drivers/video/chips/src/ct_BlitMM.h Normal file
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/* Definitions for the Chips and Technology BitBLT engine communication. */
/* These are done using Memory Mapped IO, of the registers */
/* BitBLT modes for register 93D0. */
#define ctPATCOPY 0xF0
#define ctTOP2BOTTOM 0x100
#define ctBOTTOM2TOP 0x000
#define ctLEFT2RIGHT 0x200
#define ctRIGHT2LEFT 0x000
#define ctSRCFG 0x400
#define ctSRCMONO 0x800
#define ctPATMONO 0x1000
#define ctBGTRANSPARENT 0x2000
#define ctSRCSYSTEM 0x4000
#define ctPATSOLID 0x80000L
#define ctPATSTART0 0x00000L
#define ctPATSTART1 0x10000L
#define ctPATSTART2 0x20000L
#define ctPATSTART3 0x30000L
#define ctPATSTART4 0x40000L
#define ctPATSTART5 0x50000L
#define ctPATSTART6 0x60000L
#define ctPATSTART7 0x70000L
/* Macros to do useful things with the C&T BitBLT engine */
#define ctBLTWAIT \
{HW_DEBUG(0x4); \
while(MMIO_IN32(cPtr->MMIOBase, MR(0x4)) & 0x00100000){};}
#define ctSETROP(op) \
{HW_DEBUG(0x4); MMIO_OUT32(cPtr->MMIOBase, MR(0x4), op);}
#define ctSETSRCADDR(srcAddr) \
{HW_DEBUG(0x5); \
MMIO_OUT32(cPtr->MMIOBase, MR(0x5),(srcAddr)&0x7FFFFFL);}
#define ctSETDSTADDR(dstAddr) \
{HW_DEBUG(0x6); \
MMIO_OUT32(cPtr->MMIOBase, MR(0x6), (dstAddr)&0x7FFFFFL);}
#define ctSETPITCH(srcPitch,dstPitch) \
{HW_DEBUG(0x0); \
MMIO_OUT32(cPtr->MMIOBase, MR(0x0),(((dstPitch)&0xFFFF)<<16)| \
((srcPitch)&0xFFFF));}
#define ctSETHEIGHTWIDTHGO(Height,Width)\
{HW_DEBUG(0x7); \
MMIO_OUT32(cPtr->MMIOBase, MR(0x7), (((Height)&0xFFFF)<<16)| \
((Width)&0xFFFF));}
#define ctSETPATSRCADDR(srcAddr)\
{HW_DEBUG(0x1); \
MMIO_OUT32(cPtr->MMIOBase, MR(0x1),(srcAddr)&0x1FFFFFL);}
#define ctSETBGCOLOR8(c) {\
HW_DEBUG(0x2); \
if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
cAcl->bgColor = (c); \
MMIO_OUT32(cPtr->MMIOBase, MR(0x2),\
((((((c)&0xFF)<<8)|((c)&0xFF))<<16) | \
((((c)&0xFF)<<8)|((c)&0xFF)))); \
} \
}
#define ctSETBGCOLOR16(c) {\
HW_DEBUG(0x2); \
if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
cAcl->bgColor = (c); \
MMIO_OUT32(cPtr->MMIOBase, MR(0x2), \
((((c)&0xFFFF)<<16)|((c)&0xFFFF))); \
} \
}
/* As the 6554x doesn't support 24bpp colour expansion this doesn't work,
* It is here only for later use with the 65550 */
#define ctSETBGCOLOR24(c) {\
HW_DEBUG(0x2); \
if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
cAcl->bgColor = (c); \
MMIO_OUT32(cPtr->MMIOBase, MR(0x2),((c)&0xFFFFFF)); \
} \
}
#define ctSETFGCOLOR8(c) {\
HW_DEBUG(0x3); \
if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
cAcl->fgColor = (c); \
MMIO_OUT32(cPtr->MMIOBase, MR(0x3), \
((((((c)&0xFF)<<8)|((c)&0xFF))<<16) | \
((((c)&0xFF)<<8)|((c)&0xFF)))); \
} \
}
#define ctSETFGCOLOR16(c) {\
HW_DEBUG(0x3); \
if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
cAcl->fgColor = (c); \
MMIO_OUT32(cPtr->MMIOBase, MR(0x3), \
((((c)&0xFFFF)<<16)|((c)&0xFFFF))); \
} \
}
/* As the 6554x doesn't support 24bpp colour expansion this doesn't work,
* It is here only for later use with the 65550 */
#define ctSETFGCOLOR24(c) {\
HW_DEBUG(0x3); \
if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
cAcl->fgColor = (c); \
MMIO_OUT32(cPtr->MMIOBase, MR(0x3),((c)&0xFFFFFF)); \
} \
}
/* Define a Macro to replicate a planemask 64 times and write to address
* allocated for planemask pattern */
#define ctWRITEPLANEMASK8(mask,addr) { \
if (cAcl->planemask != (mask&0xFF)) { \
cAcl->planemask = (mask&0xFF); \
memset((unsigned char *)cPtr->FbBase + addr, (mask&0xFF), 64); \
} \
}
#define ctWRITEPLANEMASK16(mask,addr) { \
if (cAcl->planemask != (mask&0xFFFF)) { \
cAcl->planemask = (mask&0xFFFF); \
{ int i; \
for (i = 0; i < 64; i++) { \
memcpy((unsigned char *)cPtr->FbBase + addr \
+ i * 2, &mask, 2); \
} \
} \
} \
}

166
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/* Definitions for the Chips and Technology BitBLT engine communication. */
/* registers */
/* Do not read 87D0 while BitBLT is active */
/* 83D0: 11-0 source offset, width of 'screen' */
/* 15-12 reserved (0) */
/* 27-16 destination offset, width of screen */
/* 31-28 reserved (0) */
/* 87D0: 20-0 pattern (aligned 8 pixel x 8 line) pointer */
/* 31-21 reserved (0) */
/* 8BD0: 15-0 background colour */
/* 31-6 duplicate of 15-0 */
/* 8FD0: 15-0 foregroud/solid colour */
/* 31-6 duplicate of 15-0 */
/* 93D0: 7-0 ROP, same as MS-Windows */
/* 8 BitBLT Y direction, if 0 bottom to top, 1 top to bottom */
/* 9 BitBLT X direction, if 0 right to left, 1 left to right */
/* 10 source data, if 0 source is selected bit 14, 1 foregourd colour */
/* 11 source depth, if 0 source is colour, */
/* 1 source is monochrome(Font expansion) */
/* 12 pattern depth, if 0 colour, else monochrome */
/* 13 background, if 0 opaque (8BD0), else transparent */
/* 14 BitBLT source, if 0 screen, else system memory */
/* 15 reserved (0, destination?) */
/* 18-16 starting row of 8x8 pattern */
/* 19 if 1 solid pattern (Brush), else bitmap */
/* 20(R) BitBLT status, if 1 active */
/* 23-21 reserved (0) */
/* 27-24 vacancy in buffer */
/* 31-25 reserved (0) */
/* 97D0: 20-0 source address (byte aligned) */
/* 31-21 reserved (0) */
/* 9BD0: 20-0 destination address (byte aligned) */
/* 31-21 reserved (0) */
/* 9FD0: 11-0 number of bytes to be transferred per line */
/* 15-12 reserved (0) */
/* 27-16 height in lines of the block to be transferred */
/* 31-28 reserved (0) */
/* BitBLT modes for register 93D0. */
#define ctPATCOPY 0xF0
#define ctTOP2BOTTOM 0x100
#define ctBOTTOM2TOP 0x000
#define ctLEFT2RIGHT 0x200
#define ctRIGHT2LEFT 0x000
#define ctSRCFG 0x400
#define ctSRCMONO 0x800
#define ctPATMONO 0x1000
#define ctBGTRANSPARENT 0x2000
#define ctSRCSYSTEM 0x4000
#define ctPATSOLID 0x80000L
#define ctPATSTART0 0x00000L
#define ctPATSTART1 0x10000L
#define ctPATSTART2 0x20000L
#define ctPATSTART3 0x30000L
#define ctPATSTART4 0x40000L
#define ctPATSTART5 0x50000L
#define ctPATSTART6 0x60000L
#define ctPATSTART7 0x70000L
/* Macros to do useful things with the C&T BitBLT engine */
#define ctBLTWAIT \
{HW_DEBUG(0x4+2); while(inw(cPtr->PIOBase+DR(0x4)+2)&0x10){};}
#define ctSETROP(op) \
{HW_DEBUG(0x4); outl(cPtr->PIOBase+DR(0x4),(op));}
#define ctSETSRCADDR(srcAddr) \
{HW_DEBUG(0x5); outl(cPtr->PIOBase+DR(0x5),((srcAddr)&0x1FFFFFL));}
#define ctSETDSTADDR(dstAddr) \
{HW_DEBUG(0x6); outl(cPtr->PIOBase+DR(0x6),((dstAddr)&0x1FFFFFL));}
#define ctSETPITCH(srcPitch,dstPitch) \
{HW_DEBUG(0x0); outl(cPtr->PIOBase+DR(0x0),(((dstPitch)<<16)|(srcPitch)));}
/* Note that this command signal a blit to commence */
#define ctSETHEIGHTWIDTHGO(Height,Width)\
{HW_DEBUG(0x7); outl(cPtr->PIOBase+DR(0x7),(((Height)<<16)|(Width)));}
#define ctSETPATSRCADDR(srcAddr)\
{HW_DEBUG(0x1); outl(cPtr->PIOBase+DR(0x1),((srcAddr)&0x1FFFFFL));}
/* I can't help pointing out at this point that I'm not complaining
* about the american spelling of Colour!! [DGB] */
#define ctSETBGCOLOR8(c) {\
HW_DEBUG(0x2); \
if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
cAcl->bgColor = (c); \
outl(cPtr->PIOBase+DR(0x2),((((((c)&0xFF)<<8)|((c)&0xFF))<<16) | \
((((c)&0xFF)<<8)|((c)&0xFF)))); \
} \
}
#define ctSETBGCOLOR16(c) {\
HW_DEBUG(0x2); \
if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
cAcl->bgColor = (c); \
outl(cPtr->PIOBase+DR(0x2),((((c)&0xFFFF)<<16)|((c)&0xFFFF))); \
} \
}
/* As the 6554x doesn't support 24bpp colour expansion this doesn't work */
#define ctSETBGCOLOR24(c) {\
HW_DEBUG(0x2); \
if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
cAcl->bgColor = (c); \
outl(cPtr->PIOBase+DR(0x2),(c)&0xFFFFFF); \
} \
}
#define ctSETFGCOLOR8(c) {\
HW_DEBUG(0x3); \
if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
cAcl->fgColor = (c); \
outl(cPtr->PIOBase+DR(0x3),((((((c)&0xFF)<<8)|((c)&0xFF))<<16) | \
((((c)&0xFF)<<8)|((c)&0xFF)))); \
} \
}
#define ctSETFGCOLOR16(c) {\
HW_DEBUG(0x3); \
if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
cAcl->fgColor = (c); \
outl(cPtr->PIOBase+DR(0x3),((((c)&0xFFFF)<<16)|((c)&0xFFFF))); \
} \
}
/* As the 6554x doesn't support 24bpp colour expansion this doesn't work */
#define ctSETFGCOLOR24(c) {\
HW_DEBUG(0x3); \
if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
cAcl->fgColor = (c); \
outl(cPtr->PIOBase+DR(0x3),(c)&0xFFFFFF); \
} \
}
/* Define a Macro to replicate a planemask 64 times and write to address
* allocated for planemask pattern */
#define ctWRITEPLANEMASK8(mask,addr) { \
if (cAcl->planemask != (mask&0xFF)) { \
cAcl->planemask = (mask&0xFF); \
memset((unsigned char *)cPtr->FbBase + addr, (mask&0xFF), 64); \
} \
}
#define ctWRITEPLANEMASK16(mask,addr) { \
if (cAcl->planemask != (mask&0xFFFF)) { \
cAcl->planemask = (mask&0xFFFF); \
{ int i; \
for (i = 0; i < 64; i++) { \
memcpy((unsigned char *)cPtr->FbBase + addr \
+ i * 2, &mask, 2); \
} \
} \
} \
}

185
hw/xfree86/drivers/video/chips/src/ct_BltHiQV.h Normal file
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/* Definitions for the Chips and Technology BitBLT engine communication. */
/* These are done using Memory Mapped IO, of the registers */
/* BitBLT modes for register 93D0. */
#define ctPATCOPY 0xF0
#define ctLEFT2RIGHT 0x000
#define ctRIGHT2LEFT 0x100
#define ctTOP2BOTTOM 0x000
#define ctBOTTOM2TOP 0x200
#define ctSRCSYSTEM 0x400
#define ctDSTSYSTEM 0x800
#define ctSRCMONO 0x1000
#define ctBGTRANSPARENT 0x22000
#define ctCOLORTRANSENABLE 0x4000
#define ctCOLORTRANSDISABLE 0x0
#define ctCOLORTRANSDST 0x8000
#define ctCOLORTRANSROP 0x0
#define ctCOLORTRANSEQUAL 0x10000L
#define ctCOLORTRANSNEQUAL 0x0
#define ctPATMONO 0x40000L
#define ctPATSOLID 0x80000L
#define ctPATSTART0 0x000000L
#define ctPATSTART1 0x100000L
#define ctPATSTART2 0x200000L
#define ctPATSTART3 0x300000L
#define ctPATSTART4 0x400000L
#define ctPATSTART5 0x500000L
#define ctPATSTART6 0x600000L
#define ctPATSTART7 0x700000L
#define ctSRCFG 0x000000L /* Where is this for the 65550?? */
/* The Monochrome expansion register setup */
#define ctCLIPLEFT(clip) ((clip)&0x3F)
#define ctCLIPRIGHT(clip) (((clip)&0x3F) << 8)
#define ctSRCDISCARD(clip) (((clip)&0x3F) << 16)
#define ctBITALIGN 0x1000000L
#define ctBYTEALIGN 0x2000000L
#define ctWORDALIGN 0x3000000L
#define ctDWORDALIGN 0x4000000L
#define ctQWORDALIGN 0x5000000L
/* This shouldn't be used because not all chip rev's
* have BR09 and BR0A, and I haven't even defined
* macros to write to these registers
*/
#define ctEXPCOLSEL 0x8000000L
/* Macros to do useful things with the C&T BitBLT engine */
/* For some odd reason the blitter busy bit occasionly "locks up" when
* it gets polled to fast. However I have observed this behavior only
* when doing ScreenToScreenColorExpandFill on a 65550. This operation
* was broken anyway (the source offset register is not observed) therefore
* no action was taken.
*
* This function uses indirect access to XR20 to test whether the blitter
* is busy. If the cost of doing this is too high then other options will
* need to be considered.
*
* Note that BR04[31] can't be used as some C&T chipsets lockup when reading
* the BRxx registers.
*/
#define ctBLTWAIT \
{int timeout; \
timeout = 0; \
for (;;) { \
if (cPtr->Chipset >= CHIPS_CT69000 ) { \
if (!(MMIO_IN32(cPtr->MMIOBase,BR(0x4))&(1<<31)))\
break; \
} else { \
if (!(cPtr->readXR(cPtr,0x20) & 0x1)) break; \
} \
timeout++; \
if ((cPtr->Chipset < CHIPS_CT69000 && \
(timeout > 100000)) || timeout > 300000) { \
unsigned char tmp; \
ErrorF("timeout\n"); \
tmp = cPtr->readXR(cPtr, 0x20); \
cPtr->writeXR(cPtr, 0x20, ((tmp & 0xFD) | 0x2)); \
usleep(10000); \
cPtr->writeXR(cPtr, 0x20, (tmp & 0xFD)); \
break; \
} \
} \
}
#if X_BYTE_ORDER == X_BIG_ENDIAN
# define TWEAK_24_BE(c) \
c = ((c & 0xFF0000) >> 16) | (c & 0xFF00) | (( c & 0xFF) << 16)
#else
# define TWEAK_24_BE(c)
#endif
#define ctSETROP(op) \
MMIO_OUT32(cPtr->MMIOBase, BR(0x4), op)
#define ctSETMONOCTL(op) \
MMIO_OUT32(cPtr->MMIOBase, BR(0x3), op)
#define ctSETSRCADDR(srcAddr) \
MMIO_OUT32(cPtr->MMIOBase, BR(0x6), (srcAddr)&0x7FFFFFL)
#define ctSETDSTADDR(dstAddr) \
MMIO_OUT32(cPtr->MMIOBase, BR(0x7), (dstAddr)&0x7FFFFFL)
#define ctSETPITCH(srcPitch,dstPitch) \
MMIO_OUT32(cPtr->MMIOBase, BR(0x0), (((dstPitch)&0xFFFF)<<16)| \
((srcPitch)&0xFFFF))
#define ctSETHEIGHTWIDTHGO(Height,Width)\
MMIO_OUT32(cPtr->MMIOBase, BR(0x8), (((Height)&0xFFFF)<<16)| \
((Width)&0xFFFF))
#define ctSETPATSRCADDR(srcAddr)\
MMIO_OUT32(cPtr->MMIOBase, BR(0x5), (srcAddr)&0x7FFFFFL)
#define ctSETBGCOLOR8(c) {\
if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
cAcl->bgColor = (c); \
MMIO_OUT32(cPtr->MMIOBase, BR(0x1), ((c)&0xFF)); \
} \
}
#define ctSETBGCOLOR16(c) {\
if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
cAcl->bgColor = (c); \
MMIO_OUT32(cPtr->MMIOBase, BR(0x1), ((c)&0xFFFF)); \
} \
}
#define ctSETBGCOLOR24(c) {\
TWEAK_24_BE(c); \
if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
cAcl->bgColor = (c); \
MMIO_OUT32(cPtr->MMIOBase, BR(0x1), ((c)&0xFFFFFF)); \
} \
}
#define ctSETFGCOLOR8(c) {\
if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
cAcl->fgColor = (c); \
MMIO_OUT32(cPtr->MMIOBase, BR(0x2), ((c)&0xFF)); \
} \
}
#define ctSETFGCOLOR16(c) {\
if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
cAcl->fgColor = (c); \
MMIO_OUT32(cPtr->MMIOBase, BR(0x2), ((c)&0xFFFF)); \
} \
}
#define ctSETFGCOLOR24(c) {\
TWEAK_24_BE(c); \
if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
cAcl->fgColor = (c); \
MMIO_OUT32(cPtr->MMIOBase, BR(0x2), ((c)&0xFFFFFF)); \
} \
}
/* Define a Macro to replicate a planemask 64 times and write to address
* allocated for planemask pattern */
#define ctWRITEPLANEMASK8(mask,addr) { \
if (cAcl->planemask != (mask&0xFF)) { \
cAcl->planemask = (mask&0xFF); \
memset((unsigned char *)cPtr->FbBase + addr, (mask&0xFF), 64); \
} \
}
#define ctWRITEPLANEMASK16(mask,addr) { \
if (cAcl->planemask != (mask&0xFFFF)) { \
cAcl->planemask = (mask&0xFFFF); \
{ int i; \
for (i = 0; i < 64; i++) { \
memcpy((unsigned char *)cPtr->FbBase + addr \
+ i * 2, &mask, 2); \
} \
} \
} \
}

80
hw/xfree86/drivers/video/chips/src/ct_accel.c Normal file
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/*
* Copyright 1996, 1997, 1998 by David Bateman <dbateman@ee.uts.edu.au>
* Modified 1997, 1998 by Nozomi Ytow
*
* Permission to use, copy, modify, distribute, and sell this software and its
* documentation for any purpose is hereby granted without fee, provided that
* the above copyright notice appear in all copies and that both that
* copyright notice and this permission notice appear in supporting
* documentation, and that the name of the authors not be used in
* advertising or publicity pertaining to distribution of the software without
* specific, written prior permission. The authors makes no representations
* about the suitability of this software for any purpose. It is provided
* "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
/*
* When monochrome tiles/stipples are cached on the HiQV chipsets the
* pitch of the monochrome data is the displayWidth. The HiQV manuals
* state that the source pitch is ignored with monochrome data, and so
* "officially" there the XAA cached monochrome data can't be used. But
* it appears that by not setting the monochrome source alignment in
* BR03, the monochrome source pitch is forced to the displayWidth!!
*
* To enable the use of this undocumented feature, uncomment the define
* below.
*/
#define UNDOCUMENTED_FEATURE
/* All drivers should typically include these */
#include "xf86.h"
#include "xf86_OSproc.h"
#include "compiler.h"
/* Drivers that need to access the PCI config space directly need this */
#include "xf86Pci.h"
/* Drivers that use XAA need this */
#include "xf86fbman.h"
/* Our driver specific include file */
#include "ct_driver.h"
#define CATNAME(prefix,subname) prefix##subname
#ifdef CHIPS_MMIO
#ifdef CHIPS_HIQV
#include "ct_BltHiQV.h"
#define CTNAME(subname) CATNAME(CHIPSHiQV,subname)
#else
#include "ct_BlitMM.h"
#define CTNAME(subname) CATNAME(CHIPSMMIO,subname)
#endif
#else
#include "ct_Blitter.h"
#define CTNAME(subname) CATNAME(CHIPS,subname)
#endif
Bool
CTNAME(AccelInit)(ScreenPtr pScreen)
{
return FALSE;
}
void
CTNAME(Sync)(ScrnInfoPtr pScrn)
{
}

629
hw/xfree86/drivers/video/chips/src/ct_bank.c Normal file
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/*
* Copyright 1997
* Digital Equipment Corporation. All rights reserved.
* This software is furnished under license and may be used and copied only in
* accordance with the following terms and conditions. Subject to these
* conditions, you may download, copy, install, use, modify and distribute
* this software in source and/or binary form. No title or ownership is
* transferred hereby.
* 1) Any source code used, modified or distributed must reproduce and retain
* this copyright notice and list of conditions as they appear in the
* source file.
*
* 2) No right is granted to use any trade name, trademark, or logo of Digital
* Equipment Corporation. Neither the "Digital Equipment Corporation" name
* nor any trademark or logo of Digital Equipment Corporation may be used
* to endorse or promote products derived from this software without the
* prior written permission of Digital Equipment Corporation.
*
* 3) This software is provided "AS-IS" and any express or implied warranties,
* including but not limited to, any implied warranties of merchantability,
* fitness for a particular purpose, or non-infringement are disclaimed. In
* no event shall DIGITAL be liable for any damages whatsoever, and in
* particular, DIGITAL shall not be liable for special, indirect,
* consequential, or incidental damages or damages for lost profits, loss
* of revenue or loss of use, whether such damages arise in contract,
* negligence, tort, under statute, in equity, at law or otherwise, even if
* advised of the possibility of such damage.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#define PSZ 8
/*
* Define DIRECT_REGISTER_ACCESS if you want to bypass the wrapped register
* access functions
*/
/* #define DIRECT_REGISTER_ACCESS */
/* All drivers should typically include these */
#include "xf86.h"
#include "xf86_OSproc.h"
/* Everything using inb/outb, etc needs "compiler.h" */
#include "compiler.h"
/* Drivers that need to access the PCI config space directly need this */
#include "xf86Pci.h"
/* Driver specific headers */
#include "ct_driver.h"
#if defined(__arm32__) && defined(__NetBSD__)
#include <machine/sysarch.h>
#define arm32_drain_writebuf() sysarch(1, 0)
#elif defined(__arm32__)
#define arm32_drain_writebuf()
#endif
#define ChipsBank(pScreen) CHIPSPTR(xf86ScreenToScrn(pScreen))->Bank
#ifdef DIRECT_REGISTER_ACCESS
int
CHIPSSetRead(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
outw(cPtr->PIOBase + 0x3D6, ((((bank << 3) & 0xFF) << 8) | 0x10));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != ChipsBank(pScreen)) {
arm32_drain_writebuf();
ChipsBank(pScreen) = bank;
}
#endif
return 0;
}
int
CHIPSSetWrite(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
outw(cPtr->PIOBase + 0x3D6, ((((bank << 3) & 0xFF) << 8) | 0x11));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != ChipsBank(pScreen)) {
arm32_drain_writebuf();
ChipsBank(pScreen) = bank;
}
#endif
return 0;
}
int
CHIPSSetReadWrite(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
outw(cPtr->PIOBase + 0x3D6, ((((bank << 3) & 0xFF) << 8) | 0x10));
outw(cPtr->PIOBase + 0x3D6, ((((bank << 3) & 0xFF) << 8) | 0x11));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != ChipsBank(pScreen)) {
arm32_drain_writebuf();
ChipsBank(pScreen) = bank;
}
#endif
return 0;
}
int
CHIPSSetReadPlanar(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
outw(cPtr->PIOBase + 0x3D6, ((((bank << 5) & 0xFF) << 8) | 0x10));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != ChipsBank(pScreen)) {
arm32_drain_writebuf();
ChipsBank(pScreen) = bank;
}
#endif
return 0;
}
int
CHIPSSetWritePlanar(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
outw(cPtr->PIOBase + 0x3D6, ((((bank << 5) & 0xFF) << 8) | 0x11));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != ChipsBank(pScreen)) {
arm32_drain_writebuf();
ChipsBank(pScreen) = bank;
}
#endif
return 0;
}
int
CHIPSSetReadWritePlanar(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
outw(cPtr->PIOBase + 0x3D6, ((((bank << 5) & 0xFF) << 8) | 0x10));
outw(cPtr->PIOBase + 0x3D6, ((((bank << 5) & 0xFF) << 8) | 0x11));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != ChipsBank(pScreen)) {
arm32_drain_writebuf();
ChipsBank(pScreen) = bank;
}
#endif
return 0;
}
int
CHIPSWINSetRead(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
register unsigned char tmp;
outw(cPtr->PIOBase + 0x3D6, ((((bank << 3) & 0xFF) << 8) | 0x10));
outb(cPtr->PIOBase + 0x3D6, 0x0C);
tmp = inb(cPtr->PIOBase + 0x3D7) & 0xEF;
outw(cPtr->PIOBase + 0x3D6, (((((bank >> 1) & 0x10) | tmp) << 8) | 0x0C));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != ChipsBank(pScreen)) {
arm32_drain_writebuf();
ChipsBank(pScreen) = bank;
}
#endif
return 0;
}
int
CHIPSWINSetWrite(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
register unsigned char tmp;
outw(cPtr->PIOBase + 0x3D6, ((((bank << 3) & 0xFF) << 8) | 0x11));
outb(cPtr->PIOBase + 0x3D6, 0x0C);
tmp = inb(cPtr->PIOBase + 0x3D7) & 0xBF;
outw(cPtr->PIOBase + 0x3D6, (((((bank << 1) & 0x40) | tmp) << 8) | 0x0C));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != ChipsBank(pScreen)) {
arm32_drain_writebuf();
ChipsBank(pScreen) = bank;
}
#endif
return 0;
}
int
CHIPSWINSetReadWrite(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
register unsigned char tmp;
outw(cPtr->PIOBase + 0x3D6, ((((bank << 3) & 0xFF) << 8) | 0x10));
outw(cPtr->PIOBase + 0x3D6, ((((bank << 3) & 0xFF) << 8) | 0x11));
outb(cPtr->PIOBase + 0x3D6, 0x0C);
tmp = inb(cPtr->PIOBase + 0x3D7) & 0xAF;
outw(cPtr->PIOBase + 0x3D6,
(((((bank << 1) & 0x40) | ((bank >> 1) & 0x10) | tmp) << 8) | 0x0C));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != ChipsBank(pScreen)) {
arm32_drain_writebuf();
ChipsBank(pScreen) = bank;
}
#endif
return 0;
}
int
CHIPSWINSetReadPlanar(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
register unsigned char tmp;
outw(cPtr->PIOBase + 0x3D6, ((((bank << 5) & 0xFF) << 8) | 0x10));
outb(cPtr->PIOBase + 0x3D6, 0x0C);
tmp = inb(cPtr->PIOBase + 0x3D7) & 0xEF;
outw(cPtr->PIOBase + 0x3D6, (((((bank << 1) & 0x10) | tmp) << 8) | 0x0C));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != ChipsBank(pScreen)) {
arm32_drain_writebuf();
ChipsBank(pScreen) = bank;
}
#endif
return 0;
}
int
CHIPSWINSetWritePlanar(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
register unsigned char tmp;
outw(cPtr->PIOBase + 0x3D6, ((((bank << 5) & 0xFF) << 8) | 0x11));
outb(cPtr->PIOBase + 0x3D6, 0x0C);
tmp = inb(cPtr->PIOBase + 0x3D7) & 0xBF;
outw(cPtr->PIOBase + 0x3D6, (((((bank << 3) & 0x40) | tmp) << 8) | 0x0C));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != ChipsBank(pScreen)) {
arm32_drain_writebuf();
ChipsBank(pScreen) = bank;
}
#endif
return 0;
}
int
CHIPSWINSetReadWritePlanar(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
register unsigned char tmp;
outw(cPtr->PIOBase + 0x3D6, ((((bank << 5) & 0xFF) << 8) | 0x10));
outw(cPtr->PIOBase + 0x3D6, ((((bank << 5) & 0xFF) << 8) | 0x11));
outb(cPtr->PIOBase + 0x3D6, 0x0C);
tmp = inb(cPtr->PIOBase + 0x3D7) & 0xAF;
outw(cPtr->PIOBase + 0x3D6,
(((((bank << 3) & 0x40) | ((bank << 1) & 0x10) | tmp) << 8) | 0x0C));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != ChipsBank(pScreen)) {
arm32_drain_writebuf();
ChipsBank(pScreen) = bank;
}
#endif
return 0;
}
int
CHIPSHiQVSetReadWrite(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
outw(cPtr->PIOBase + 0x3D6, (((bank & 0x7F) << 8) | 0x0E));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != ChipsBank(pScreen)) {
arm32_drain_writebuf();
ChipsBank(pScreen) = bank;
}
#endif
return 0;
}
int
CHIPSHiQVSetReadWritePlanar(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
outw(cPtr->PIOBase + 0x3D6, ((((bank << 2) & 0x7F) << 8) | 0x0E));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != ChipsBank(pScreen)) {
arm32_drain_writebuf();
ChipsBank(pScreen) = bank;
}
#endif
return 0;
}
#else /* DIRECT_REGISTER_ACCESS */
int
CHIPSSetRead(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
cPtr->writeXR(cPtr, 0x10, ((bank << 3) & 0xFF));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != cPtr->Bank) {
arm32_drain_writebuf();
cPtr->Bank = bank;
}
#endif
return 0;
}
int
CHIPSSetWrite(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
cPtr->writeXR(cPtr, 0x11, ((bank << 3) & 0xFF));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != cPtr->Bank) {
arm32_drain_writebuf();
cPtr->Bank = bank;
}
#endif
return 0;
}
int
CHIPSSetReadWrite(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
cPtr->writeXR(cPtr, 0x10, ((bank << 3) & 0xFF));
cPtr->writeXR(cPtr, 0x11, ((bank << 3) & 0xFF));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != cPtr->Bank) {
arm32_drain_writebuf();
cPtr->Bank = bank;
}
#endif
return 0;
}
int
CHIPSSetReadPlanar(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
cPtr->writeXR(cPtr, 0x10, ((bank << 5) & 0xFF));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != cPtr->Bank) {
arm32_drain_writebuf();
cPtr->Bank = bank;
}
#endif
return 0;
}
int
CHIPSSetWritePlanar(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
cPtr->writeXR(cPtr, 0x11, ((bank << 5) & 0xFF));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != cPtr->Bank) {
arm32_drain_writebuf();
cPtr->Bank = bank;
}
#endif
return 0;
}
int
CHIPSSetReadWritePlanar(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
cPtr->writeXR(cPtr, 0x10, ((bank << 5) & 0xFF));
cPtr->writeXR(cPtr, 0x11, ((bank << 5) & 0xFF));
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != cPtr->Bank) {
arm32_drain_writebuf();
cPtr->Bank = bank;
}
#endif
return 0;
}
int
CHIPSWINSetRead(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
register unsigned char tmp;
cPtr->writeXR(cPtr, 0x10, ((bank << 3) & 0xFF));
tmp = cPtr->readXR(cPtr, 0x0C) & 0xEF;
cPtr->writeXR(cPtr, 0x0C, ((bank >> 1) & 0x10) | tmp);
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != cPtr->Bank) {
arm32_drain_writebuf();
cPtr->Bank = bank;
}
#endif
return 0;
}
int
CHIPSWINSetWrite(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
register unsigned char tmp;
cPtr->writeXR(cPtr, 0x11, ((bank << 3) & 0xFF));
tmp = cPtr->readXR(cPtr, 0x0C) & 0xBF;
cPtr->writeXR(cPtr, 0x0C, ((bank << 1) & 0x40) | tmp);
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != cPtr->Bank) {
arm32_drain_writebuf();
cPtr->Bank = bank;
}
#endif
return 0;
}
int
CHIPSWINSetReadWrite(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
register unsigned char tmp;
cPtr->writeXR(cPtr, 0x10, ((bank << 3) & 0xFF));
cPtr->writeXR(cPtr, 0x11, ((bank << 3) & 0xFF));
tmp = cPtr->readXR(cPtr, 0x0C) & 0xAF;
cPtr->writeXR(cPtr, 0x0C, ((bank << 1) & 0x40) | ((bank >> 1) & 0x10) | tmp);
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != cPtr->Bank) {
arm32_drain_writebuf();
cPtr->Bank = bank;
}
#endif
return 0;
}
int
CHIPSWINSetReadPlanar(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
register unsigned char tmp;
cPtr->writeXR(cPtr, 0x10, ((bank << 5) & 0xFF));
tmp = cPtr->readXR(cPtr, 0x0C) & 0xEF;
cPtr->writeXR(cPtr, 0x0C, ((bank << 1) & 0x10) | tmp);
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != cPtr->Bank) {
arm32_drain_writebuf();
cPtr->Bank = bank;
}
#endif
return 0;
}
int
CHIPSWINSetWritePlanar(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
register unsigned char tmp;
cPtr->writeXR(cPtr, 0x11, ((bank << 5) & 0xFF));
tmp = cPtr->readXR(cPtr, 0x0C) & 0xBF;
cPtr->writeXR(cPtr, 0x0C, ((bank << 3) & 0x40) | tmp);
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != cPtr->Bank) {
arm32_drain_writebuf();
cPtr->Bank = bank;
}
#endif
return 0;
}
int
CHIPSWINSetReadWritePlanar(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
register unsigned char tmp;
cPtr->writeXR(cPtr, 0x10, ((bank << 5) & 0xFF));
cPtr->writeXR(cPtr, 0x11, ((bank << 5) & 0xFF));
tmp = cPtr->readXR(cPtr, 0x0C) & 0xAF;
cPtr->writeXR(cPtr, 0x0C, ((bank << 3) & 0x40) | ((bank << 1) & 0x10) | tmp);
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != cPtr->Bank) {
arm32_drain_writebuf();
cPtr->Bank = bank;
}
#endif
return 0;
}
int
CHIPSHiQVSetReadWrite(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
cPtr->writeXR(cPtr, 0x0E, bank & 0x7F);
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != cPtr->Bank) {
arm32_drain_writebuf();
cPtr->Bank = bank;
}
#endif
return 0;
}
int
CHIPSHiQVSetReadWritePlanar(ScreenPtr pScreen, int bank)
{
CHIPSPtr cPtr = CHIPSPTR(xf86ScreenToScrn(pScreen));
cPtr->writeXR(cPtr, 0x0E, (bank << 2) & 0x7F);
#ifdef __arm32__
/* Must drain StrongARM write buffer on bank switch! */
if (bank != cPtr->Bank) {
arm32_drain_writebuf();
cPtr->Bank = bank;
}
#endif
return 0;
}
#endif

475
hw/xfree86/drivers/video/chips/src/ct_cursor.c Normal file
View File

@@ -0,0 +1,475 @@
/*
* Copyright 1994 The XFree86 Project
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* DAVID WEXELBLAT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Hardware Cursor for Trident utilizing XAA Cursor code.
* Written by Alan Hourihane <alanh@fairlite.demon.co.uk>
* Modified for Chips and Technologies by David Bateman <dbateman@eng.uts.edu.au>
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
/* All drivers should typically include these */
#include "xf86.h"
#include "xf86_OSproc.h"
/* Everything using inb/outb, etc needs "compiler.h" */
#include "compiler.h"
/* Drivers that need to access the PCI config space directly need this */
#include "xf86Pci.h"
#include "xf86Cursor.h"
/* Driver specific headers */
#include "ct_driver.h"
/* Sync function, maybe this should check infoRec->NeedToSync before syncing */
#define CURSOR_SYNC(pScrn)
/* Swing your cursor bytes round and round... yeehaw! */
#if X_BYTE_ORDER == X_BIG_ENDIAN
#define P_SWAP32( a , b ) \
((char *)a)[0] = ((char *)b)[3]; \
((char *)a)[1] = ((char *)b)[2]; \
((char *)a)[2] = ((char *)b)[1]; \
((char *)a)[3] = ((char *)b)[0]
#define P_SWAP16( a , b ) \
((char *)a)[0] = ((char *)b)[1]; \
((char *)a)[1] = ((char *)b)[0]; \
((char *)a)[2] = ((char *)b)[3]; \
((char *)a)[3] = ((char *)b)[2]
#endif
static void
CHIPSShowCursor(ScrnInfoPtr pScrn)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
unsigned char tmp;
CURSOR_SYNC(pScrn);
/* turn the cursor on */
if (IS_HiQV(cPtr)) {
tmp = cPtr->readXR(cPtr, 0xA0);
cPtr->writeXR(cPtr, 0xA0, (tmp & 0xF8) | 5);
if (cPtr->UseDualChannel &&
(! xf86IsEntityShared(pScrn->entityList[0]))) {
unsigned int IOSS, MSS;
IOSS = cPtr->readIOSS(cPtr);
MSS = cPtr->readMSS(cPtr);
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
IOSS_PIPE_B));
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &
MSS_MASK) | MSS_PIPE_B));
tmp = cPtr->readXR(cPtr, 0xA0);
cPtr->writeXR(cPtr, 0xA0, (tmp & 0xF8) | 5);
cPtr->writeIOSS(cPtr, IOSS);
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), MSS);
}
} else {
if(!cPtr->UseMMIO) {
HW_DEBUG(0x8);
outw(cPtr->PIOBase+DR(0x8), 0x21);
} else {
HW_DEBUG(DR(8));
/* Used to be: MMIOmemw(MR(8)) = 0x21; */
MMIOmeml(MR(8)) = 0x21;
}
}
cPtr->HWCursorShown = TRUE;
}
static void
CHIPSHideCursor(ScrnInfoPtr pScrn)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
unsigned char tmp;
CURSOR_SYNC(pScrn);
/* turn the cursor off */
if (IS_HiQV(cPtr)) {
tmp = cPtr->readXR(cPtr, 0xA0);
cPtr->writeXR(cPtr, 0xA0, tmp & 0xF8);
if (cPtr->UseDualChannel &&
(! xf86IsEntityShared(pScrn->entityList[0]))) {
unsigned int IOSS, MSS;
IOSS = cPtr->readIOSS(cPtr);
MSS = cPtr->readMSS(cPtr);
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
IOSS_PIPE_B));
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &
MSS_MASK) | MSS_PIPE_B));
tmp = cPtr->readXR(cPtr, 0xA0);
cPtr->writeXR(cPtr, 0xA0, tmp & 0xF8);
cPtr->writeIOSS(cPtr, IOSS);
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), MSS);
}
} else {
if(!cPtr->UseMMIO) {
HW_DEBUG(0x8);
outw(cPtr->PIOBase+DR(0x8), 0x20);
} else {
HW_DEBUG(DR(0x8));
/* Used to be: MMIOmemw(DR(0x8)) = 0x20; */
MMIOmeml(DR(0x8)) = 0x20;
}
}
cPtr->HWCursorShown = FALSE;
}
static void
CHIPSSetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CURSOR_SYNC(pScrn);
if (x < 0)
x = ~(x-1) | 0x8000;
if (y < 0)
y = ~(y-1) | 0x8000;
/* Program the cursor origin (offset into the cursor bitmap). */
if (IS_HiQV(cPtr)) {
cPtr->writeXR(cPtr, 0xA4, x & 0xFF);
cPtr->writeXR(cPtr, 0xA5, (x >> 8) & 0x87);
cPtr->writeXR(cPtr, 0xA6, y & 0xFF);
cPtr->writeXR(cPtr, 0xA7, (y >> 8) & 0x87);
if (cPtr->UseDualChannel &&
(! xf86IsEntityShared(pScrn->entityList[0]))) {
unsigned int IOSS, MSS;
IOSS = cPtr->readIOSS(cPtr);
MSS = cPtr->readMSS(cPtr);
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
IOSS_PIPE_B));
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &
MSS_MASK) | MSS_PIPE_B));
cPtr->writeXR(cPtr, 0xA4, x & 0xFF);
cPtr->writeXR(cPtr, 0xA5, (x >> 8) & 0x87);
cPtr->writeXR(cPtr, 0xA6, y & 0xFF);
cPtr->writeXR(cPtr, 0xA7, (y >> 8) & 0x87);
cPtr->writeIOSS(cPtr, IOSS);
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), MSS);
}
} else {
CARD32 xy;
xy = y;
xy = (xy << 16) | x;
if(!cPtr->UseMMIO) {
HW_DEBUG(0xB);
outl(cPtr->PIOBase+DR(0xB), xy);
} else {
HW_DEBUG(MR(0xB));
MMIOmeml(MR(0xB)) = xy;
}
}
}
static void
CHIPSSetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
vgaHWPtr hwp = VGAHWPTR(pScrn);
CARD32 packedcolfg, packedcolbg;
CURSOR_SYNC(pScrn);
if (IS_HiQV(cPtr)) {
unsigned char xr80;
/* Enable extended palette addressing */
xr80 = cPtr->readXR(cPtr, 0x80);
cPtr->writeXR(cPtr, 0x80, xr80 | 0x1);
/* Write the new colours to the extended VGA palette. Palette
* index is incremented after each write, so only write index
* once
*/
hwp->writeDacWriteAddr(hwp, 0x04);
if (xr80 & 0x80) {
/* 8bit DAC */
hwp->writeDacData(hwp, (bg >> 16) & 0xFF);
hwp->writeDacData(hwp, (bg >> 8) & 0xFF);
hwp->writeDacData(hwp, bg & 0xFF);
hwp->writeDacData(hwp, (fg >> 16) & 0xFF);
hwp->writeDacData(hwp, (fg >> 8) & 0xFF);
hwp->writeDacData(hwp, fg & 0xFF);
} else {
/* 6bit DAC */
hwp->writeDacData(hwp, (bg >> 18) & 0xFF);
hwp->writeDacData(hwp, (bg >> 10) & 0xFF);
hwp->writeDacData(hwp, (bg >> 2) & 0xFF);
hwp->writeDacData(hwp, (fg >> 18) & 0xFF);
hwp->writeDacData(hwp, (fg >> 10) & 0xFF);
hwp->writeDacData(hwp, (fg >> 2) & 0xFF);
}
/* Enable normal palette addressing */
cPtr->writeXR(cPtr, 0x80, xr80);
if (cPtr->UseDualChannel &&
(! xf86IsEntityShared(pScrn->entityList[0]))) {
unsigned int IOSS, MSS;
IOSS = cPtr->readIOSS(cPtr);
MSS = cPtr->readMSS(cPtr);
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
IOSS_PIPE_B));
cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) |
MSS_PIPE_B));
/* Enable extended palette addressing */
xr80 = cPtr->readXR(cPtr, 0x80);
cPtr->writeXR(cPtr, 0x80, xr80 | 0x1);
/* Write the new colours to the extended VGA palette. Palette
* index is incremented after each write, so only write index
* once
*/
hwp->writeDacWriteAddr(hwp, 0x04);
if (xr80 & 0x80) {
/* 8bit DAC */
hwp->writeDacData(hwp, (bg >> 16) & 0xFF);
hwp->writeDacData(hwp, (bg >> 8) & 0xFF);
hwp->writeDacData(hwp, bg & 0xFF);
hwp->writeDacData(hwp, (fg >> 16) & 0xFF);
hwp->writeDacData(hwp, (fg >> 8) & 0xFF);
hwp->writeDacData(hwp, fg & 0xFF);
} else {
/* 6bit DAC */
hwp->writeDacData(hwp, (bg >> 18) & 0xFF);
hwp->writeDacData(hwp, (bg >> 10) & 0xFF);
hwp->writeDacData(hwp, (bg >> 2) & 0xFF);
hwp->writeDacData(hwp, (fg >> 18) & 0xFF);
hwp->writeDacData(hwp, (fg >> 10) & 0xFF);
hwp->writeDacData(hwp, (fg >> 2) & 0xFF);
}
/* Enable normal palette addressing */
cPtr->writeXR(cPtr, 0x80, xr80);
cPtr->writeIOSS(cPtr, IOSS);
cPtr->writeMSS(cPtr, hwp, MSS);
}
} else if (IS_Wingine(cPtr)) {
outl(cPtr->PIOBase+DR(0xA), (bg & 0xFFFFFF));
outl(cPtr->PIOBase+DR(0x9), (fg & 0xFFFFFF));
} else {
packedcolfg = ((fg & 0xF80000) >> 8) | ((fg & 0xFC00) >> 5)
| ((fg & 0xF8) >> 3);
packedcolbg = ((bg & 0xF80000) >> 8) | ((bg & 0xFC00) >> 5)
| ((bg & 0xF8) >> 3);
packedcolfg = (packedcolfg << 16) | packedcolbg;
if(!cPtr->UseMMIO) {
HW_DEBUG(0x9);
outl(cPtr->PIOBase+DR(0x9), packedcolfg);
} else {
MMIOmeml(MR(0x9)) = packedcolfg;
HW_DEBUG(MR(0x9));
}
}
}
static void
CHIPSLoadCursorImage(ScrnInfoPtr pScrn, unsigned char *src)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSACLPtr cAcl = CHIPSACLPTR(pScrn);
#if X_BYTE_ORDER == X_BIG_ENDIAN
CARD32 *s = (pointer)src;
CARD32 *d = (pointer)(cPtr->FbBase + cAcl->CursorAddress);
int y;
#endif
CURSOR_SYNC(pScrn);
if (cPtr->cursorDelay) {
usleep(200000);
cPtr->cursorDelay = FALSE;
}
if (IS_Wingine(cPtr)) {
int i;
CARD32 *tmp = (CARD32 *)src;
outl(cPtr->PIOBase+DR(0x8),0x20);
for (i=0; i<64; i++) {
outl(cPtr->PIOBase+DR(0xC),*(CARD32 *)tmp);
tmp++;
}
} else {
if (cPtr->Flags & ChipsLinearSupport) {
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* On big endian machines we must flip our cursor image around. */
switch(pScrn->bitsPerPixel >> 3) {
case 4:
case 3:
#if 1
memcpy((unsigned char *)cPtr->FbBase + cAcl->CursorAddress,
src, cPtr->CursorInfoRec->MaxWidth *
cPtr->CursorInfoRec->MaxHeight / 4);
#else
for (y = 0; y < 64; y++) {
P_SWAP32(d,s);
d++; s++;
P_SWAP32(d,s);
d++; s++;
P_SWAP32(d,s);
d++; s++;
P_SWAP32(d,s);
d++; s++;
}
#endif
break;
case 2:
for (y = 0; y < 64; y++) {
P_SWAP16(d,s);
d++; s++;
P_SWAP16(d,s);
d++; s++;
P_SWAP16(d,s);
d++; s++;
P_SWAP16(d,s);
d++; s++;
}
break;
default:
for (y = 0; y < 64; y++) {
*d++ = *s++;
*d++ = *s++;
*d++ = *s++;
*d++ = *s++;
}
}
#else
memcpy((unsigned char *)cPtr->FbBase + cAcl->CursorAddress,
src, cPtr->CursorInfoRec->MaxWidth *
cPtr->CursorInfoRec->MaxHeight / 4);
#endif
} else {
/*
* The cursor can only be in the last 16K of video memory,
* which fits in the last banking window.
*/
if (IS_HiQV(cPtr))
if (pScrn->bitsPerPixel < 8)
CHIPSHiQVSetReadWritePlanar(pScrn->pScreen,
(int)(cAcl->CursorAddress >> 16));
else
CHIPSHiQVSetReadWrite(pScrn->pScreen,
(int)(cAcl->CursorAddress >> 16));
else
if (pScrn->bitsPerPixel < 8)
CHIPSSetWritePlanar(pScrn->pScreen,
(int)(cAcl->CursorAddress >> 16));
else
CHIPSSetWrite(pScrn->pScreen,
(int)(cAcl->CursorAddress >> 16));
memcpy((unsigned char *)cPtr->FbBase + (cAcl->CursorAddress &
0xFFFF), src, cPtr->CursorInfoRec->MaxWidth *
cPtr->CursorInfoRec->MaxHeight / 4);
}
}
/* set cursor address here or we loose the cursor on video mode change */
if (IS_HiQV(cPtr)) {
cPtr->writeXR(cPtr, 0xA2, (cAcl->CursorAddress >> 8) & 0xFF);
cPtr->writeXR(cPtr, 0xA3, (cAcl->CursorAddress >> 16) & 0x3F);
if (cPtr->UseDualChannel &&
(! xf86IsEntityShared(pScrn->entityList[0]))) {
unsigned int IOSS, MSS;
IOSS = cPtr->readIOSS(cPtr);
MSS = cPtr->readMSS(cPtr);
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
IOSS_PIPE_B));
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &
MSS_MASK) | MSS_PIPE_B));
cPtr->writeXR(cPtr, 0xA2, (cAcl->CursorAddress >> 8) & 0xFF);
cPtr->writeXR(cPtr, 0xA3, (cAcl->CursorAddress >> 16) & 0x3F);
cPtr->writeIOSS(cPtr, IOSS);
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), MSS);
}
} else if (!IS_Wingine(cPtr)) {
if (!cPtr->UseMMIO) {
HW_DEBUG(0xC);
outl(cPtr->PIOBase+DR(0xC), cAcl->CursorAddress);
} else {
HW_DEBUG(MR(0xC));
MMIOmeml(MR(0xC)) = cAcl->CursorAddress;
}
}
}
static Bool
CHIPSUseHWCursor(ScreenPtr pScreen, CursorPtr pCurs)
{
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
return (((cPtr->Flags & ChipsHWCursor) != 0)
&& !(pScrn->currentMode->Flags & V_DBLSCAN));
}
Bool
CHIPSCursorInit(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
xf86CursorInfoPtr infoPtr;
infoPtr = xf86CreateCursorInfoRec();
if(!infoPtr) return FALSE;
cPtr->CursorInfoRec = infoPtr;
infoPtr->Flags =
#if X_BYTE_ORDER == X_LITTLE_ENDIAN
HARDWARE_CURSOR_BIT_ORDER_MSBFIRST |
#endif
HARDWARE_CURSOR_INVERT_MASK |
HARDWARE_CURSOR_SWAP_SOURCE_AND_MASK |
HARDWARE_CURSOR_TRUECOLOR_AT_8BPP;
if (IS_HiQV(cPtr)) {
infoPtr->Flags |= HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_64;
infoPtr->MaxHeight = 64;
infoPtr->MaxWidth = 64;
} else if (IS_Wingine(cPtr)) {
infoPtr->Flags |= HARDWARE_CURSOR_SOURCE_MASK_NOT_INTERLEAVED;
infoPtr->MaxHeight = 32;
infoPtr->MaxWidth = 32;
} else {
infoPtr->Flags |= HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_8;
infoPtr->MaxHeight = 32;
infoPtr->MaxWidth = 32;
}
infoPtr->SetCursorColors = CHIPSSetCursorColors;
infoPtr->SetCursorPosition = CHIPSSetCursorPosition;
infoPtr->LoadCursorImage = CHIPSLoadCursorImage;
infoPtr->HideCursor = CHIPSHideCursor;
infoPtr->ShowCursor = CHIPSShowCursor;
infoPtr->UseHWCursor = CHIPSUseHWCursor;
return(xf86InitCursor(pScreen, infoPtr));
}

287
hw/xfree86/drivers/video/chips/src/ct_ddc.c Normal file
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#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
/* All drivers should typically include these */
#include "xf86.h"
#include "xf86_OSproc.h"
/* Everything using inb/outb, etc needs "compiler.h" */
#include "compiler.h"
/* Drivers that need to access the PCI config space directly need this */
#include "xf86Pci.h"
#include "ct_driver.h"
static Bool chips_TestI2C(int scrnIndex);
static Bool chips_setI2CBits(I2CBusPtr I2CPtr, ScrnInfoPtr pScrn);
static unsigned int
chips_ddc1Read(ScrnInfoPtr pScrn)
{
unsigned char ddc_mask = ((CHIPSPtr)pScrn->driverPrivate)->ddc_mask;
CHIPSPtr cPtr = CHIPSPTR(pScrn);
vgaHWPtr hwp = VGAHWPTR(pScrn);
register unsigned int tmp;
while ((hwp->readST01(hwp)) & 0x08){};
while (!((hwp->readST01(hwp)) & 0x08)){};
tmp = cPtr->readXR(cPtr, 0x63);
return (tmp & ddc_mask);
}
static void
chips_ddc1SetSpeed(ScrnInfoPtr pScrn, xf86ddcSpeed speed)
{
vgaHWddc1SetSpeed(pScrn, speed);
}
void
chips_ddc1(ScrnInfoPtr pScrn)
{
unsigned char FR0B, FR0C, XR62;
unsigned char mask_c = 0x00;
unsigned char val, tmp_val = 0;
int i;
CHIPSPtr cPtr = CHIPSPTR(pScrn);
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Probing for DDC1\n");
FR0C = cPtr->readFR(cPtr, 0x0C);
XR62 = cPtr->readXR(cPtr, 0x62);
switch (cPtr->Chipset) {
case CHIPS_CT65550:
cPtr->ddc_mask = 0x1F; /* GPIO 0-4 */
FR0B = cPtr->readFR(cPtr, 0x0B);
if (!(FR0B & 0x10)) /* GPIO 2 is used as 32 kHz input */
cPtr->ddc_mask &= 0xFB;
if (cPtr->Bus == ChipsVLB) /* GPIO 3-7 are used as address bits */
cPtr->ddc_mask &= 0x07;
break;
case CHIPS_CT65554:
case CHIPS_CT65555:
case CHIPS_CT68554:
cPtr->ddc_mask = 0x0F; /* GPIO 0-3 */
break;
case CHIPS_CT69000:
case CHIPS_CT69030:
cPtr->ddc_mask = 0x9F; /* GPIO 0-4,7? */
break;
default:
cPtr->ddc_mask = 0x0C; /* GPIO 2,3 */
break;
}
if (!(FR0C & 0x80)) { /* GPIO 1 is not available */
mask_c |= 0xC0;
cPtr->ddc_mask &= 0xFE;
}
if (!(FR0C & 0x10)) { /* GPIO 0 is not available */
mask_c |= 0x18;
cPtr->ddc_mask &= 0xFD;
}
/* set GPIO 0,1 to read if available */
cPtr->writeFR(cPtr, 0x0C, (FR0C & mask_c) | (~mask_c & 0x90));
/* set remaining GPIO to read */
cPtr->writeXR(cPtr, 0x62, 0x00);
val = chips_ddc1Read(pScrn);
for (i = 0; i < 70; i++) {
tmp_val = chips_ddc1Read(pScrn);
if (tmp_val != val)
break;
}
cPtr->ddc_mask = val ^ tmp_val;
if (cPtr->ddc_mask)
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "DDC1 found\n");
else return;
xf86PrintEDID(xf86DoEDID_DDC1(XF86_SCRN_ARG(pScrn), chips_ddc1SetSpeed,
chips_ddc1Read));
/* restore */
cPtr->writeFR(cPtr, 0x0C, FR0C);
cPtr->writeXR(cPtr, 0x62, XR62);
}
static void
chips_I2CGetBits(I2CBusPtr b, int *clock, int *data)
{
CHIPSI2CPtr pI2C_c = (CHIPSI2CPtr) (b->DriverPrivate.ptr);
unsigned char FR0C, XR62, val;
FR0C = pI2C_c->cPtr->readFR(pI2C_c->cPtr, 0x0C);
if (pI2C_c->i2cDataBit & 0x01 || pI2C_c->i2cClockBit & 0x01)
FR0C = (FR0C & 0xE7) | 0x10;
if (pI2C_c->i2cDataBit & 0x02 || pI2C_c->i2cClockBit & 0x02)
FR0C = (FR0C & 0x3F) | 0x80;
XR62 = pI2C_c->cPtr->readXR(pI2C_c->cPtr, 0x62);
XR62 &= (~pI2C_c->i2cDataBit) & (~pI2C_c->i2cClockBit);
pI2C_c->cPtr->writeFR(pI2C_c->cPtr, 0x0C, FR0C);
pI2C_c->cPtr->writeXR(pI2C_c->cPtr, 0x62, XR62);
val = pI2C_c->cPtr->readXR(pI2C_c->cPtr, 0x63);
*clock = (val & pI2C_c->i2cClockBit) != 0;
*data = (val & pI2C_c->i2cDataBit) != 0;
}
static void
chips_I2CPutBits(I2CBusPtr b, int clock, int data)
{
CHIPSI2CPtr pI2C_c = (CHIPSI2CPtr) (b->DriverPrivate.ptr);
unsigned char FR0C, XR62, val;
FR0C = pI2C_c->cPtr->readFR(pI2C_c->cPtr, 0x0C);
if (((pI2C_c->i2cDataBit & 0x01) && data)
|| ((pI2C_c->i2cClockBit & 0x01) && clock))
FR0C |= 0x18;
else if ((pI2C_c->i2cDataBit & 0x01)
|| (pI2C_c->i2cClockBit & 0x01))
FR0C |= 0x10;
if (((pI2C_c->i2cDataBit & 0x02) && data)
|| ((pI2C_c->i2cClockBit & 0x02) && clock))
FR0C |= 0xC0;
else if ((pI2C_c->i2cDataBit & 0x02)
|| (pI2C_c->i2cClockBit & 0x02))
FR0C |= 0x80;
XR62 = pI2C_c->cPtr->readXR(pI2C_c->cPtr, 0x62);
XR62 = (XR62 & ~pI2C_c->i2cClockBit) | (clock ? pI2C_c->i2cClockBit : 0);
XR62 = (XR62 & ~pI2C_c->i2cDataBit) | (data ? pI2C_c->i2cDataBit : 0);
pI2C_c->cPtr->writeFR(pI2C_c->cPtr, 0x0C, FR0C);
pI2C_c->cPtr->writeXR(pI2C_c->cPtr, 0x62, XR62);
val = pI2C_c->cPtr->readXR(pI2C_c->cPtr, 0x63);
val = (val & ~pI2C_c->i2cClockBit) | (clock ? pI2C_c->i2cClockBit : 0);
val = (val & ~pI2C_c->i2cDataBit) | (data ? pI2C_c->i2cDataBit : 0);
pI2C_c->cPtr->writeXR(pI2C_c->cPtr, 0x63, val);
}
Bool
chips_i2cInit(ScrnInfoPtr pScrn)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
I2CBusPtr I2CPtr;
I2CPtr = xf86CreateI2CBusRec();
if(!I2CPtr) return FALSE;
cPtr->I2C = I2CPtr;
I2CPtr->BusName = "DDC";
I2CPtr->scrnIndex = pScrn->scrnIndex;
I2CPtr->I2CPutBits = chips_I2CPutBits;
I2CPtr->I2CGetBits = chips_I2CGetBits;
I2CPtr->DriverPrivate.ptr = malloc(sizeof(CHIPSI2CRec));
((CHIPSI2CPtr)(I2CPtr->DriverPrivate.ptr))->cPtr = cPtr;
if (!xf86I2CBusInit(I2CPtr))
return FALSE;
if (!chips_setI2CBits(I2CPtr, pScrn))
return FALSE;
return TRUE;
}
static Bool
chips_setI2CBits(I2CBusPtr b, ScrnInfoPtr pScrn)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSI2CPtr pI2C_c = (CHIPSI2CPtr) (b->DriverPrivate.ptr);
unsigned char FR0B, FR0C;
unsigned char bits, data_bits, clock_bits;
int i,j;
FR0C = cPtr->readFR(cPtr, 0x0C);
switch (cPtr->Chipset) {
case CHIPS_CT65550:
bits = 0x1F; /* GPIO 0-4 */
FR0B = cPtr->readFR(cPtr, 0x0B);
if (!(FR0B & 0x10)) /* GPIO 2 is used as 32 kHz input */
bits &= 0xFB;
pI2C_c->i2cDataBit = 0x01;
pI2C_c->i2cClockBit = 0x02;
if (cPtr->Bus == ChipsVLB) /* GPIO 3-7 are used as address bits */
bits &= 0x07;
break;
case CHIPS_CT65554:
case CHIPS_CT65555:
case CHIPS_CT68554:
bits = 0x0F; /* GPIO 0-3 */
pI2C_c->i2cDataBit = 0x04;
pI2C_c->i2cClockBit = 0x08;
break;
case CHIPS_CT69000:
case CHIPS_CT69030:
bits = 0x9F; /* GPIO 0-4,7? */
pI2C_c->i2cDataBit = 0x04;
pI2C_c->i2cClockBit = 0x08;
break;
default:
bits = 0x0C; /* GPIO 2,3 */
pI2C_c->i2cDataBit = 0x04;
pI2C_c->i2cClockBit = 0x08;
break;
}
if (!(FR0C & 0x80)) { /* GPIO 1 is not available */
bits &= 0xFE;
}
if (!(FR0C & 0x10)) { /* GPIO 0 is not available */
bits &= 0xFD;
}
pI2C_c->i2cClockBit &= bits;
pI2C_c->i2cDataBit &= bits;
/*
* first we test out the "favorite" GPIO bits ie. the ones suggested
* by the data book; if we don't succeed test all other combinations
* of possible GPIO pins as data/clock lines as the manufacturer might
* have its own ideas.
*/
if (chips_TestI2C(pScrn->scrnIndex)) return TRUE;
data_bits = bits;
pI2C_c->i2cDataBit = 0x01;
for (i = 0; i<8; i++) {
if (data_bits & 0x01) {
clock_bits = bits;
pI2C_c->i2cClockBit = 0x01;
for (j = 0; j<8; j++) {
if (clock_bits & 0x01)
if (chips_TestI2C(pScrn->scrnIndex)) return TRUE;
clock_bits >>= 1;
pI2C_c->i2cClockBit <<= 1;
}
}
data_bits >>= 1;
pI2C_c->i2cDataBit <<= 1;
}
/*
* We haven't found a valid clock/data line combination - that
* doesn't mean there aren't any. We just haven't received an
* answer from the relevant DDC I2C addresses. We'll have to wait
* and see, if this is too restrictive (eg one wants to use I2C
* for something else than DDC we might have to probe more addresses
* or just fall back to the "favorite" GPIO lines.
*/
return FALSE;
}
static Bool
chips_TestI2C(int scrnIndex)
{
int i;
I2CBusPtr b;
b = xf86I2CFindBus(scrnIndex, "DDC");
if (b == NULL) return FALSE;
else {
for(i = 0xA0; i < 0xA8; i += 2)
if(xf86I2CProbeAddress(b, i))
return TRUE;
}
return FALSE;
}

235
hw/xfree86/drivers/video/chips/src/ct_dga.c Normal file
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#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86.h"
#include "xf86_OSproc.h"
#include "xf86Pci.h"
#include "ct_driver.h"
#include "dgaproc.h"
static Bool CHIPS_OpenFramebuffer(ScrnInfoPtr, char **, unsigned char **,
int *, int *, int *);
static Bool CHIPS_SetMode(ScrnInfoPtr, DGAModePtr);
static int CHIPS_GetViewport(ScrnInfoPtr);
static void CHIPS_SetViewport(ScrnInfoPtr, int, int, int);
static
DGAFunctionRec CHIPS_DGAFuncs = {
CHIPS_OpenFramebuffer,
NULL,
CHIPS_SetMode,
CHIPS_SetViewport,
CHIPS_GetViewport,
NULL, NULL, NULL, NULL
};
static
DGAFunctionRec CHIPS_MMIODGAFuncs = {
CHIPS_OpenFramebuffer,
NULL,
CHIPS_SetMode,
CHIPS_SetViewport,
CHIPS_GetViewport,
NULL, NULL, NULL, NULL
};
static
DGAFunctionRec CHIPS_HiQVDGAFuncs = {
CHIPS_OpenFramebuffer,
NULL,
CHIPS_SetMode,
CHIPS_SetViewport,
CHIPS_GetViewport,
NULL, NULL, NULL, NULL
};
Bool
CHIPSDGAInit(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
DGAModePtr modes = NULL, newmodes = NULL, currentMode;
DisplayModePtr pMode, firstMode;
int Bpp = pScrn->bitsPerPixel >> 3;
int num = 0;
Bool oneMore;
int imlines = (pScrn->videoRam * 1024) /
(pScrn->displayWidth * (pScrn->bitsPerPixel >> 3));
pMode = firstMode = pScrn->modes;
while(pMode) {
if(0 /*pScrn->displayWidth != pMode->HDisplay*/) {
newmodes = realloc(modes, (num + 2) * sizeof(DGAModeRec));
oneMore = TRUE;
} else {
newmodes = realloc(modes, (num + 1) * sizeof(DGAModeRec));
oneMore = FALSE;
}
if(!newmodes) {
free(modes);
return FALSE;
}
modes = newmodes;
SECOND_PASS:
currentMode = modes + num;
num++;
currentMode->mode = pMode;
currentMode->flags = DGA_CONCURRENT_ACCESS | DGA_PIXMAP_AVAILABLE;
if(pMode->Flags & V_DBLSCAN)
currentMode->flags |= DGA_DOUBLESCAN;
if(pMode->Flags & V_INTERLACE)
currentMode->flags |= DGA_INTERLACED;
currentMode->byteOrder = pScrn->imageByteOrder;
currentMode->depth = pScrn->depth;
currentMode->bitsPerPixel = pScrn->bitsPerPixel;
currentMode->red_mask = pScrn->mask.red;
currentMode->green_mask = pScrn->mask.green;
currentMode->blue_mask = pScrn->mask.blue;
currentMode->visualClass = (Bpp == 1) ? PseudoColor : TrueColor;
currentMode->viewportWidth = pMode->HDisplay;
currentMode->viewportHeight = pMode->VDisplay;
currentMode->xViewportStep = 1;
currentMode->yViewportStep = 1;
currentMode->viewportFlags = DGA_FLIP_RETRACE | DGA_FLIP_IMMEDIATE;
currentMode->offset = 0;
currentMode->address = cPtr->FbBase;
if(oneMore) { /* first one is narrow width */
currentMode->bytesPerScanline = ((pMode->HDisplay * Bpp) + 3) & ~3L;
currentMode->imageWidth = pMode->HDisplay;
currentMode->imageHeight = imlines;
currentMode->pixmapWidth = currentMode->imageWidth;
currentMode->pixmapHeight = currentMode->imageHeight;
currentMode->maxViewportX = currentMode->imageWidth -
currentMode->viewportWidth;
/* this might need to get clamped to some maximum */
currentMode->maxViewportY = currentMode->imageHeight -
currentMode->viewportHeight;
oneMore = FALSE;
goto SECOND_PASS;
} else {
currentMode->bytesPerScanline =
((pScrn->displayWidth * Bpp) + 3) & ~3L;
currentMode->imageWidth = pScrn->displayWidth;
currentMode->imageHeight = imlines;
currentMode->pixmapWidth = currentMode->imageWidth;
currentMode->pixmapHeight = currentMode->imageHeight;
currentMode->maxViewportX = currentMode->imageWidth -
currentMode->viewportWidth;
/* this might need to get clamped to some maximum */
currentMode->maxViewportY = currentMode->imageHeight -
currentMode->viewportHeight;
}
pMode = pMode->next;
if(pMode == firstMode)
break;
}
cPtr->numDGAModes = num;
cPtr->DGAModes = modes;
if (IS_HiQV(cPtr)) {
return DGAInit(pScreen, &CHIPS_HiQVDGAFuncs, modes, num);
} else {
if(!cPtr->UseMMIO) {
return DGAInit(pScreen, &CHIPS_DGAFuncs, modes, num);
} else {
return DGAInit(pScreen, &CHIPS_MMIODGAFuncs, modes, num);
}
}
}
static Bool
CHIPS_SetMode(
ScrnInfoPtr pScrn,
DGAModePtr pMode
){
static int OldDisplayWidth[MAXSCREENS];
int index = pScrn->pScreen->myNum;
CHIPSPtr cPtr = CHIPSPTR(pScrn);
if (!pMode) { /* restore the original mode */
/* put the ScreenParameters back */
if (cPtr->DGAactive) {
pScrn->displayWidth = OldDisplayWidth[index];
pScrn->EnterVT(VT_FUNC_ARGS);
cPtr->DGAactive = FALSE;
}
} else {
if(!cPtr->DGAactive) { /* save the old parameters */
OldDisplayWidth[index] = pScrn->displayWidth;
pScrn->LeaveVT(VT_FUNC_ARGS);
cPtr->DGAactive = TRUE;
}
pScrn->displayWidth = pMode->bytesPerScanline /
(pMode->bitsPerPixel >> 3);
CHIPSSwitchMode(SWITCH_MODE_ARGS(pScrn, pMode->mode));
}
return TRUE;
}
static int
CHIPS_GetViewport(
ScrnInfoPtr pScrn
){
CHIPSPtr cPtr = CHIPSPTR(pScrn);
return cPtr->DGAViewportStatus;
}
static void
CHIPS_SetViewport(
ScrnInfoPtr pScrn,
int x, int y,
int flags
){
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
if (flags & DGA_FLIP_RETRACE) {
while ((hwp->readST01(hwp)) & 0x08){};
while (!((hwp->readST01(hwp)) & 0x08)){};
}
CHIPSAdjustFrame(ADJUST_FRAME_ARGS(pScrn, x, y));
cPtr->DGAViewportStatus = 0; /* CHIPSAdjustFrame loops until finished */
}
static Bool
CHIPS_OpenFramebuffer(
ScrnInfoPtr pScrn,
char **name,
unsigned char **mem,
int *size,
int *offset,
int *flags
){
CHIPSPtr cPtr = CHIPSPTR(pScrn);
*name = NULL; /* no special device */
*mem = (unsigned char*)cPtr->FbAddress;
*size = cPtr->FbMapSize;
*offset = 0;
*flags = DGA_NEED_ROOT;
return TRUE;
}

7315
hw/xfree86/drivers/video/chips/src/ct_driver.c Normal file
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File diff suppressed because it is too large Load Diff

565
hw/xfree86/drivers/video/chips/src/ct_driver.h Normal file
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/*
* Modified 1996 by Egbert Eich <eich@xfree86.org>
* Modified 1996 by David Bateman <dbateman@club-internet.fr>
*
* Permission to use, copy, modify, distribute, and sell this software and its
* documentation for any purpose is hereby granted without fee, provided that
* the above copyright notice appear in all copies and that both that
* copyright notice and this permission notice appear in supporting
* documentation, and that the name of the authors not be used in
* advertising or publicity pertaining to distribution of the software without
* specific, written prior permission. The authors makes no representations
* about the suitability of this software for any purpose. It is provided
* "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _CT_DRIVER_H_
#define _CT_DRIVER_H_
#include "config.h"
#include "ct_pcirename.h"
#include "exa.h"
#include "vbe.h"
#include "xf86Cursor.h"
#include "xf86i2c.h"
#include "xf86DDC.h"
#include "xf86xv.h"
#include "vgaHW.h"
#include <string.h>
#include <unistd.h>
#include "compat-api.h"
/* Supported chipsets */
typedef enum {
CHIPS_CT65520,
CHIPS_CT65525,
CHIPS_CT65530,
CHIPS_CT65535,
CHIPS_CT65540,
CHIPS_CT65545,
CHIPS_CT65546,
CHIPS_CT65548,
CHIPS_CT65550,
CHIPS_CT65554,
CHIPS_CT65555,
CHIPS_CT68554,
CHIPS_CT69000,
CHIPS_CT69030,
CHIPS_CT64200,
CHIPS_CT64300
} CHIPSType;
/* Clock related */
typedef struct {
unsigned char msr; /* Dot Clock Related */
unsigned char fcr;
unsigned char xr02;
unsigned char xr03;
unsigned char xr33;
unsigned char xr54;
unsigned char fr03;
int Clock;
int FPClock;
} CHIPSClockReg, *CHIPSClockPtr;
typedef struct {
unsigned int ProbedClk;
unsigned int Max; /* Memory Clock Related */
unsigned int Clk;
unsigned char M;
unsigned char N;
unsigned char P;
unsigned char PSN;
unsigned char xrCC;
unsigned char xrCD;
unsigned char xrCE;
} CHIPSMemClockReg, *CHIPSMemClockPtr;
#define TYPE_HW 0x01
#define TYPE_PROGRAMMABLE 0x02
#define GET_TYPE 0x0F
#define OLD_STYLE 0x10
#define NEW_STYLE 0x20
#define HiQV_STYLE 0x30
#define WINGINE_1_STYLE 0x40 /* 64300: external clock; 4 clocks */
#define WINGINE_2_STYLE 0x50 /* 64300: internal clock; 2 hw-clocks */
#define GET_STYLE 0xF0
#define LCD_TEXT_CLK_FREQ 25000 /* lcd textclock if TYPE_PROGRAMMABLE */
#define CRT_TEXT_CLK_FREQ 28322 /* crt textclock if TYPE_PROGRAMMABLE */
#define Fref 14318180 /* The reference clock in Hertz */
/* The capability flags for the C&T chipsets */
#define ChipsLinearSupport 0x00000001
#define ChipsAccelSupport 0x00000002
#define ChipsFullMMIOSupport 0x00000004
#define ChipsMMIOSupport 0x00000008
#define ChipsHDepthSupport 0x00000010
#define ChipsDPMSSupport 0x00000020
#define ChipsTMEDSupport 0x00000040
#define ChipsGammaSupport 0x00000080
#define ChipsVideoSupport 0x00000100
#define ChipsDualChannelSupport 0x00000200
#define ChipsDualRefresh 0x00000400
#define Chips64BitMemory 0x00000800
/* Options flags for the C&T chipsets */
#define ChipsHWCursor 0x00001000
#define ChipsShadowFB 0x00002000
#define ChipsUseNewFB 0x00008000
/* Architecture type flags */
#define ChipsHiQV 0x00010000
#define ChipsWingine 0x00020000
#define IS_Wingine(x) ((x->Flags) & ChipsWingine)
#define IS_HiQV(x) ((x->Flags) & ChipsHiQV)
/* Acceleration flags for the C&T chipsets */
#define ChipsColorTransparency 0x0100000
#define ChipsImageReadSupport 0x0200000
/* Overlay Transparency Key */
#define TRANSPARENCY_KEY 255
/* Flag Bus Types */
#define ChipsUnknown 0
#define ChipsISA 1
#define ChipsVLB 2
#define ChipsPCI 3
#define ChipsCPUDirect 4
#define ChipsPIB 5
#define ChipsMCB 6
/* Macro's to select the 32 bit acceleration registers */
#define DR(x) cPtr->Regs32[x] /* For CT655xx naming scheme */
#define MR(x) cPtr->Regs32[x] /* CT655xx MMIO naming scheme */
#define BR(x) cPtr->Regs32[x] /* For HiQV naming scheme */
#define MMIOmeml(x) *(CARD32 *)(cPtr->MMIOBase + (x))
#if 0
#define MMIOmemw(x) *(CARD16 *)(cPtr->MMIOBase + (x))
#endif
/* Monitor or flat panel type flags */
#define ChipsCRT 0x0010
#define ChipsLCD 0x1000
#define ChipsLCDProbed 0x2000
#define ChipsTFT 0x0100
#define ChipsDS 0x0200
#define ChipsDD 0x0400
#define ChipsSS 0x0800
#define IS_STN(x) ((x) & 0xE00)
/* Dual channel register enable masks */
#define IOSS_MASK 0xE0
#define IOSS_BOTH 0x13
#define IOSS_PIPE_A 0x11
#define IOSS_PIPE_B 0x1E
#define MSS_MASK 0xF0
#define MSS_BOTH 0x0B
#define MSS_PIPE_A 0x02
#define MSS_PIPE_B 0x05
/* Aggregate value of MSS shadow bits -GHB */
#define MSS_SHADOW 0x07
/* Storage for the registers of the C&T chipsets */
typedef struct {
unsigned char XR[0xFF];
unsigned char CR[0x80];
unsigned char FR[0x80];
unsigned char MR[0x80];
CHIPSClockReg Clock;
} CHIPSRegRec, *CHIPSRegPtr;
/* Storage for the flat panel size */
typedef struct {
int HDisplay;
int HRetraceStart;
int HRetraceEnd;
int HTotal;
int VDisplay;
int VRetraceStart;
int VTotal;
} CHIPSPanelSizeRec, *CHIPSPanelSizePtr;
/* Some variables needed in the XAA acceleration */
typedef struct {
/* General variable */
unsigned int CommandFlags;
unsigned int BytesPerPixel;
unsigned int BitsPerPixel;
unsigned int FbOffset;
unsigned int PitchInBytes;
unsigned int ScratchAddress;
/* 64k for color expansion and imagewrites */
unsigned char * BltDataWindow;
/* Hardware cursor address */
unsigned int CursorAddress;
Bool UseHWCursor;
/* Boundaries of the pixmap cache */
unsigned int CacheStart;
unsigned int CacheEnd;
/* Storage for pattern mask */
int planemask;
int srcpitch, srcoffset, xdir, ydir;
/* Storage for foreground and background color */
int fgColor;
int bgColor;
/* For the 8x8 pattern fills */
int patternyrot;
/* For cached stipple fills */
int SlotWidth;
/* Variables for the 24bpp fill */
unsigned char fgpixel;
unsigned char bgpixel;
unsigned char xorpixel;
Bool fastfill;
Bool rgb24equal;
int fillindex;
unsigned int width24bpp;
unsigned int color24bpp;
unsigned int rop24bpp;
} CHIPSACLRec, *CHIPSACLPtr;
#define CHIPSACLPTR(p) &((CHIPSPtr)((p)->driverPrivate))->Accel
/* Storage for some register values that are messed up by suspend/resumes */
typedef struct {
unsigned char xr02;
unsigned char xr03;
unsigned char xr14;
unsigned char xr15;
unsigned char vgaIOBaseFlag;
} CHIPSSuspendHackRec, *CHIPSSuspendHackPtr;
/* The functions to access the C&T extended registers */
typedef struct _CHIPSRec *CHIPSPtr;
typedef CARD8 (*chipsReadXRPtr)(CHIPSPtr cPtr, CARD8 index);
typedef void (*chipsWriteXRPtr)(CHIPSPtr cPtr, CARD8 index, CARD8 value);
typedef CARD8 (*chipsReadFRPtr)(CHIPSPtr cPtr, CARD8 index);
typedef void (*chipsWriteFRPtr)(CHIPSPtr cPtr, CARD8 index, CARD8 value);
typedef CARD8 (*chipsReadMRPtr)(CHIPSPtr cPtr, CARD8 index);
typedef void (*chipsWriteMRPtr)(CHIPSPtr cPtr, CARD8 index, CARD8 value);
typedef CARD8 (*chipsReadMSSPtr)(CHIPSPtr cPtr);
typedef void (*chipsWriteMSSPtr)(CHIPSPtr cPtr, vgaHWPtr hwp, CARD8 value);
typedef CARD8 (*chipsReadIOSSPtr)(CHIPSPtr cPtr);
typedef void (*chipsWriteIOSSPtr)(CHIPSPtr cPtr, CARD8 value);
/* The privates of the C&T driver */
#define CHIPSPTR(p) ((CHIPSPtr)((p)->driverPrivate))
typedef struct {
int lastInstance;
int refCount;
CARD32 masterFbAddress;
long masterFbMapSize;
CARD32 slaveFbAddress;
long slaveFbMapSize;
int mastervideoRam;
int slavevideoRam;
Bool masterOpen;
Bool slaveOpen;
Bool masterActive;
Bool slaveActive;
} CHIPSEntRec, *CHIPSEntPtr;
typedef struct _CHIPSRec {
pciVideoPtr PciInfo;
#ifndef XSERVER_LIBPCIACCESS
PCITAG PciTag;
#endif
int Chipset;
EntityInfoPtr pEnt;
unsigned long PIOBase;
unsigned long IOAddress;
unsigned long FbAddress;
unsigned int IOBase;
unsigned char * FbBase;
unsigned char * MMIOBase;
unsigned char * MMIOBaseVGA;
unsigned char * MMIOBasePipeA;
unsigned char * MMIOBasePipeB;
long FbMapSize;
unsigned char * ShadowPtr;
int ShadowPitch;
int Rotate;
void (*PointerMoved)(SCRN_ARG_TYPE arg, int x, int y);
int FbOffset16;
int FbSize16;
OptionInfoPtr Options;
CHIPSPanelSizeRec PanelSize;
int FrameBufferSize;
Bool SyncResetIgn;
Bool UseMMIO;
Bool UseFullMMIO;
Bool UseDualChannel;
int Monitor;
int MinClock;
int MaxClock;
CHIPSClockReg SaveClock; /* Storage for ClockSelect */
CHIPSMemClockReg MemClock;
unsigned char ClockType;
unsigned char CRTClk[4];
unsigned char FPClk[4];
int FPclock;
int FPclkInx;
int CRTclkInx;
Bool FPClkModified;
int ClockMulFactor;
int Rounding;
CHIPSSuspendHackRec SuspendHack;
CARD32 PanelType;
CHIPSRegRec ModeReg;
CHIPSRegRec SavedReg;
CHIPSRegRec SavedReg2;
vgaRegRec VgaSavedReg2;
unsigned int * Regs32;
unsigned int Flags;
CARD32 Bus;
ExaDriverPtr pExa;
xf86CursorInfoPtr CursorInfoRec;
CHIPSACLRec Accel;
unsigned int HWCursorContents;
Bool HWCursorShown;
DGAModePtr DGAModes;
int numDGAModes;
Bool DGAactive;
int DGAViewportStatus;
CloseScreenProcPtr CloseScreen;
ScreenBlockHandlerProcPtr BlockHandler;
void (*VideoTimerCallback)(ScrnInfoPtr, Time);
int videoKey;
XF86VideoAdaptorPtr adaptor;
int OverlaySkewX;
int OverlaySkewY;
int VideoZoomMax;
Bool SecondCrtc;
CHIPSEntPtr entityPrivate;
unsigned char storeMSS;
unsigned char storeIOSS;
#ifdef __arm__
#ifdef __NetBSD__
int TVMode;
#endif
int Bank;
#endif
unsigned char ddc_mask;
I2CBusPtr I2C;
vbeInfoPtr pVbe;
chipsReadXRPtr readXR;
chipsWriteXRPtr writeXR;
chipsReadFRPtr readFR;
chipsWriteFRPtr writeFR;
chipsReadMRPtr readMR;
chipsWriteMRPtr writeMR;
chipsReadMSSPtr readMSS;
chipsWriteMSSPtr writeMSS;
chipsReadIOSSPtr readIOSS;
chipsWriteIOSSPtr writeIOSS;
Bool cursorDelay;
unsigned int viewportMask;
Bool dualEndianAp;
} CHIPSRec;
typedef struct _CHIPSi2c {
unsigned char i2cClockBit;
unsigned char i2cDataBit;
CHIPSPtr cPtr;
} CHIPSI2CRec, *CHIPSI2CPtr;
/* External variables */
extern int ChipsAluConv[];
extern int ChipsAluConv2[];
extern int ChipsAluConv3[];
extern unsigned int ChipsReg32[];
extern unsigned int ChipsReg32HiQV[];
/* Prototypes */
void CHIPSAdjustFrame(ADJUST_FRAME_ARGS_DECL);
Bool CHIPSSwitchMode(SWITCH_MODE_ARGS_DECL);
/* video */
void CHIPSInitVideo(ScreenPtr pScreen);
void CHIPSResetVideo(ScrnInfoPtr pScrn);
/* banking */
int CHIPSSetRead(ScreenPtr pScreen, int bank);
int CHIPSSetWrite(ScreenPtr pScreen, int bank);
int CHIPSSetReadWrite(ScreenPtr pScreen, int bank);
int CHIPSSetReadPlanar(ScreenPtr pScreen, int bank);
int CHIPSSetWritePlanar(ScreenPtr pScreen, int bank);
int CHIPSSetReadWritePlanar(ScreenPtr pScreen, int bank);
int CHIPSWINSetRead(ScreenPtr pScreen, int bank);
int CHIPSWINSetWrite(ScreenPtr pScreen, int bank);
int CHIPSWINSetReadWrite(ScreenPtr pScreen, int bank);
int CHIPSWINSetReadPlanar(ScreenPtr pScreen, int bank);
int CHIPSWINSetWritePlanar(ScreenPtr pScreen, int bank);
int CHIPSWINSetReadWritePlanar(ScreenPtr pScreen, int bank);
int CHIPSHiQVSetReadWrite(ScreenPtr pScreen, int bank);
int CHIPSHiQVSetReadWritePlanar(ScreenPtr pScreen, int bank);
/* acceleration */
Bool CHIPSAccelInit(ScreenPtr pScreen);
void CHIPSSync(ScrnInfoPtr pScrn);
Bool CHIPSMMIOAccelInit(ScreenPtr pScreen);
void CHIPSMMIOSync(ScrnInfoPtr pScrn);
Bool CHIPSHiQVAccelInit(ScreenPtr pScreen);
void CHIPSHiQVSync(ScrnInfoPtr pScrn);
Bool CHIPSCursorInit(ScreenPtr pScreen);
Bool CHIPSInitEXA(ScreenPtr pScreen);
/* register access functions */
void CHIPSSetStdExtFuncs(CHIPSPtr cPtr);
void CHIPSSetMmioExtFuncs(CHIPSPtr cPtr);
void CHIPSHWSetMmioFuncs(ScrnInfoPtr pScrn, CARD8 *base, int offset);
/* ddc */
extern void chips_ddc1(ScrnInfoPtr pScrn);
extern Bool chips_i2cInit(ScrnInfoPtr pScrn);
/* dga */
Bool CHIPSDGAInit(ScreenPtr pScreen);
/* shadow fb */
void chipsRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
void chipsRefreshArea8(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
void chipsRefreshArea16(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
void chipsRefreshArea24(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
void chipsRefreshArea32(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
void chipsPointerMoved(SCRN_ARG_TYPE arg, int x, int y);
#if X_BYTE_ORDER == X_BIG_ENDIAN
# define BE_SWAP_APRETURE(pScrn,cPtr) \
((pScrn->bitsPerPixel == 16) && cPtr->dualEndianAp)
#endif
/*
* Some macros for switching display channels. NOTE... It appears that we
* can't write to both display channels at the same time, and so the options
* MSS_BOTH and IOSS_BOTH should not be used. Need to get around this by set
* dual channel mode to pipe A by default and handling multiple channel writes
* in ModeInit..
*/
#define DUALOPEN \
{ \
/* Set the IOSS/MSS registers to point to the right register set */ \
if (xf86IsEntityShared(pScrn->entityList[0])) { \
if (cPtr->SecondCrtc == TRUE) { \
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | \
IOSS_PIPE_B)); \
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS & \
MSS_MASK) | MSS_PIPE_B)); \
cPtrEnt->slaveOpen = TRUE; \
cPtrEnt->slaveActive = TRUE; \
cPtrEnt->masterActive = FALSE; \
} else { \
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | \
IOSS_PIPE_A)); \
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS & \
MSS_MASK) | MSS_PIPE_A)); \
cPtrEnt->masterOpen = TRUE; \
cPtrEnt->masterActive = TRUE; \
cPtrEnt->slaveActive = FALSE; \
} \
} else { \
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | \
IOSS_PIPE_A)); \
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS & \
MSS_MASK) | MSS_PIPE_A)); \
} \
}
#define DUALREOPEN \
{ \
if (xf86IsEntityShared(pScrn->entityList[0])) { \
if (cPtr->SecondCrtc == TRUE) { \
if (! cPtrEnt->slaveActive) { \
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | \
IOSS_PIPE_B)); \
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS & \
MSS_MASK) | MSS_PIPE_B)); \
cPtrEnt->slaveOpen = TRUE; \
cPtrEnt->slaveActive = TRUE; \
cPtrEnt->masterActive = FALSE; \
} \
} else { \
if (! cPtrEnt->masterActive) { \
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | \
IOSS_PIPE_A)); \
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS & \
MSS_MASK) | MSS_PIPE_A)); \
cPtrEnt->masterOpen = TRUE; \
cPtrEnt->masterActive = TRUE; \
cPtrEnt->slaveActive = FALSE; \
} \
} \
} \
}
#define DUALCLOSE \
{ \
if (! xf86IsEntityShared(pScrn->entityList[0])) { \
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | \
IOSS_PIPE_A)); \
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS & \
MSS_MASK) | MSS_PIPE_A)); \
chipsHWCursorOff(cPtr, pScrn); \
chipsRestore(pScrn, &(VGAHWPTR(pScrn))->SavedReg, \
&cPtr->SavedReg, TRUE); \
chipsLock(pScrn); \
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | \
IOSS_PIPE_B)); \
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS & \
MSS_MASK) | MSS_PIPE_B)); \
chipsHWCursorOff(cPtr, pScrn); \
chipsRestore(pScrn, &cPtr->VgaSavedReg2, &cPtr->SavedReg2, TRUE); \
cPtr->writeIOSS(cPtr, cPtr->storeIOSS); \
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), cPtr->storeMSS); \
chipsLock(pScrn); \
} else { \
chipsHWCursorOff(cPtr, pScrn); \
chipsRestore(pScrn, &(VGAHWPTR(pScrn))->SavedReg, &cPtr->SavedReg,\
TRUE); \
if (cPtr->SecondCrtc == TRUE) { \
cPtrEnt->slaveActive = FALSE; \
cPtrEnt->slaveOpen = FALSE; \
if (! cPtrEnt->masterActive) { \
cPtr->writeIOSS(cPtr, cPtr->storeIOSS); \
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), cPtr->storeMSS); \
chipsLock(pScrn); \
} \
} else { \
cPtrEnt->masterActive = FALSE; \
cPtrEnt->masterOpen = FALSE; \
if (! cPtrEnt->slaveActive) { \
cPtr->writeIOSS(cPtr, cPtr->storeIOSS); \
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), cPtr->storeMSS); \
chipsLock(pScrn); \
} \
} \
} \
}
/* To aid debugging of 32 bit register access we make the following defines */
/*
#define DEBUG
#define CT_HW_DEBUG
*/
#if defined(DEBUG) & defined(CT_HW_DEBUG)
#define HW_DEBUG(x) {usleep(500000); ErrorF("Register/Address: 0x%X\n",x);}
#else
#define HW_DEBUG(x)
#endif
#endif

329
hw/xfree86/drivers/video/chips/src/ct_exa.c Normal file
View File

@@ -0,0 +1,329 @@
/*
* EXA acceleration for now ct65550 only, for lack of other hardware
*
* Copyright (C) 2016 Michael Lorenz
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* MICHAEL LORENZ BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/* $NetBSD: ct_exa.c,v 1.3 2017/02/16 15:05:57 macallan Exp $ */
#include <sys/types.h>
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
/* All drivers should typically include these */
#include "xf86.h"
#include "xf86_OSproc.h"
/* Everything using inb/outb, etc needs "compiler.h" */
#include "compiler.h"
#include "ct_driver.h"
#include "ct_BltHiQV.h"
#ifdef DEBUG
#define ENTER xf86Msg(X_ERROR, "%s\n", __func__)
#define LEAVE xf86Msg(X_ERROR, "%s done\n", __func__)
int last_op = 0, lx, ly, lw, lh, dx, dy, xdir, ydir, lsp, ldp;
#else
#define ENTER
#define LEAVE
#endif
static void
ctWaitMarker(ScreenPtr pScreen, int Marker)
{
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
ENTER;
ctBLTWAIT;
}
static int
ctMarkSync(ScreenPtr pScreenInfo)
{
ENTER;
return 0;
}
static Bool
ctPrepareCopy
(
PixmapPtr pSrcPixmap,
PixmapPtr pDstPixmap,
int xdir,
int ydir,
int alu,
Pixel planemask
)
{
ScrnInfoPtr pScrn = xf86Screens[pDstPixmap->drawable.pScreen->myNum];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSACLPtr cAcl = CHIPSACLPTR(pScrn);
ENTER;
ctBLTWAIT;
cAcl->srcpitch = exaGetPixmapPitch(pSrcPixmap);
cAcl->srcoffset = exaGetPixmapOffset(pSrcPixmap);
cAcl->xdir = xdir;
cAcl->ydir = ydir;
ctSETROP(ChipsAluConv[alu & 0xF] | ((xdir < 0) ? ctRIGHT2LEFT : 0) |
((ydir < 0) ? ctBOTTOM2TOP : 0) |
ctPATSOLID/* | ctPATMONO*/);
ctSETMONOCTL(ctDWORDALIGN);
ctSETPITCH(cAcl->srcpitch, exaGetPixmapPitch(pDstPixmap));
LEAVE;
return TRUE;
}
static void
ctCopy
(
PixmapPtr pDstPixmap,
int srcX,
int srcY,
int dstX,
int dstY,
int w,
int h
)
{
ScrnInfoPtr pScrn = xf86Screens[pDstPixmap->drawable.pScreen->myNum];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSACLPtr cAcl = CHIPSACLPTR(pScrn);
int src = cAcl->srcoffset;
int dst = exaGetPixmapOffset(pDstPixmap);
int dstpitch = exaGetPixmapPitch(pDstPixmap);
if (cAcl->ydir < 0) {
srcY += (h - 1);
dstY += (h - 1);
}
if (cAcl->xdir < 0) {
srcX += (w - 1);
dstX += (w - 1);
}
src += srcX * cAcl->BytesPerPixel + srcY * cAcl->srcpitch;
dst += dstX * cAcl->BytesPerPixel + dstY * dstpitch;
ctBLTWAIT;
ctSETSRCADDR(src);
ctSETDSTADDR(dst);
ctSETHEIGHTWIDTHGO(h, w * cAcl->BytesPerPixel);
LEAVE;
#ifdef DEBUG
last_op = 1;
lx = srcX;
ly = srcY;
lw = w;
lh = h;
dx = dstX;
dy = dstY;
xdir = cAcl->xdir;
ydir = cAcl->ydir;
lsp = cAcl->srcpitch;
ldp = dstpitch;
#endif
}
static void
ctDoneCopy(PixmapPtr pDstPixmap)
{
ENTER;
ScrnInfoPtr pScrn = xf86Screens[pDstPixmap->drawable.pScreen->myNum];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSACLPtr cAcl = CHIPSACLPTR(pScrn);
ctBLTWAIT;
LEAVE;
}
static Bool
ctPrepareSolid(
PixmapPtr pPixmap,
int alu,
Pixel planemask,
Pixel fg)
{
ScrnInfoPtr pScrn = xf86Screens[pPixmap->drawable.pScreen->myNum];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSACLPtr cAcl = CHIPSACLPTR(pScrn);
int pitch = exaGetPixmapPitch(pPixmap);
ENTER;
ctBLTWAIT;
ctSETPITCH(pitch, pitch);
ctSETROP(ChipsAluConv2[alu & 0xF] | ctPATSOLID | ctPATMONO);
ctSETMONOCTL(ctDWORDALIGN);
ctSETBGCOLOR24(fg);
LEAVE;
return TRUE;
}
static void
ctSolid(
PixmapPtr pPixmap,
int x1,
int y1,
int x2,
int y2)
{
ScrnInfoPtr pScrn = xf86Screens[pPixmap->drawable.pScreen->myNum];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSACLPtr cAcl = CHIPSACLPTR(pScrn);
int dst = exaGetPixmapOffset(pPixmap);
ENTER;
ctBLTWAIT;
dst += x1 * cAcl->BytesPerPixel + y1 * exaGetPixmapPitch(pPixmap);
ctSETDSTADDR(dst);
ctSETSRCADDR(dst);
ctSETHEIGHTWIDTHGO(y2 - y1, (x2 - x1) * cAcl->BytesPerPixel);
LEAVE;
#ifdef DEBUG
last_op = 2;
#endif
}
/*
* Memcpy-based UTS.
*/
static Bool
ctUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
char *src, int src_pitch)
{
ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
unsigned char *dst = cPtr->FbBase + exaGetPixmapOffset(pDst);
int dst_pitch = exaGetPixmapPitch(pDst);
int bpp = pDst->drawable.bitsPerPixel;
int cpp = (bpp + 7) / 8;
int wBytes = w * cpp;
ENTER;
ctBLTWAIT;
dst += (x * cpp) + (y * dst_pitch);
while (h--) {
memcpy(dst, src, wBytes);
src += src_pitch;
dst += dst_pitch;
}
LEAVE;
return TRUE;
}
/*
* Memcpy-based DFS.
*/
static Bool
ctDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w, int h,
char *dst, int dst_pitch)
{
ScrnInfoPtr pScrn = xf86Screens[pSrc->drawable.pScreen->myNum];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
unsigned char *src = cPtr->FbBase + exaGetPixmapOffset(pSrc);
int src_pitch = exaGetPixmapPitch(pSrc);
int bpp = pSrc->drawable.bitsPerPixel;
int cpp = (bpp + 7) / 8;
int wBytes = w * cpp;
ENTER;
ctBLTWAIT;
src += (x * cpp) + (y * src_pitch);
while (h--) {
memcpy(dst, src, wBytes);
src += src_pitch;
dst += dst_pitch;
}
LEAVE;
return TRUE;
}
Bool
CHIPSInitEXA(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSACLPtr cAcl = CHIPSACLPTR(pScrn);
ExaDriverPtr pExa;
pExa = exaDriverAlloc();
if (!pExa)
return FALSE;
cPtr->pExa = pExa;
#if 0
cPtr->writeXR(cPtr, 0x20, 0); /* XXX blitter in 8bit mode */
#endif
cAcl->BytesPerPixel = pScrn->bitsPerPixel >> 3;
cAcl->BitsPerPixel = pScrn->bitsPerPixel;
cAcl->planemask = -1;
cAcl->bgColor = -1;
cAcl->fgColor = -1;
cAcl->FbOffset = 0;
pExa->exa_major = EXA_VERSION_MAJOR;
pExa->exa_minor = EXA_VERSION_MINOR;
pExa->memoryBase = cPtr->FbBase;
pExa->offScreenBase = cAcl->CacheStart;
pExa->memorySize = cAcl->CacheEnd;
/*
* Contrary to the manual, the blitter needs 8 byte pitch alignment or it
* will lock up. Probably shouldn't be surprised, there are hidden 64bit
* alignment requirements all over the place.
*/
pExa->pixmapOffsetAlign = 8;
pExa->pixmapPitchAlign = 8;
pExa->flags = EXA_OFFSCREEN_PIXMAPS;
/* entirely bogus since the chip doesn't use coordinates */
pExa->maxX = 2048;
pExa->maxY = 2048;
pExa->MarkSync = ctMarkSync;
pExa->WaitMarker = ctWaitMarker;
pExa->PrepareSolid = ctPrepareSolid;
pExa->Solid = ctSolid;
pExa->DoneSolid = ctDoneCopy;
pExa->PrepareCopy = ctPrepareCopy;
pExa->Copy = ctCopy;
pExa->DoneCopy = ctDoneCopy;
/* EXA hits more optimized paths when it does not have to fallback because
* of missing UTS/DFS, hook memcpy-based UTS/DFS.
*/
pExa->UploadToScreen = ctUploadToScreen;
pExa->DownloadFromScreen = ctDownloadFromScreen;
return exaDriverInit(pScreen, pExa);
}

122
hw/xfree86/drivers/video/chips/src/ct_pcirename.h Normal file
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/*
* Copyright 2007 George Sapountzis
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/**
* Macros for porting drivers from legacy xfree86 PCI code to the pciaccess
* library. The main purpose being to facilitate source code compatibility.
*/
#ifndef CIRPCIRENAME_H
#define CIRPCIRENAME_H
enum region_type {
REGION_MEM,
REGION_IO
};
#ifndef XSERVER_LIBPCIACCESS
/* pciVideoPtr */
#define PCI_DEV_VENDOR_ID(_pcidev) ((_pcidev)->vendor)
#define PCI_DEV_DEVICE_ID(_pcidev) ((_pcidev)->chipType)
#define PCI_DEV_REVISION(_pcidev) ((_pcidev)->chipRev)
#define PCI_SUB_VENDOR_ID(_pcidev) ((_pcidev)->subsysVendor)
#define PCI_SUB_DEVICE_ID(_pcidev) ((_pcidev)->subsysCard)
#define PCI_DEV_TAG(_pcidev) pciTag((_pcidev)->bus, \
(_pcidev)->device, \
(_pcidev)->func)
#define PCI_DEV_BUS(_pcidev) ((_pcidev)->bus)
#define PCI_DEV_DEV(_pcidev) ((_pcidev)->device)
#define PCI_DEV_FUNC(_pcidev) ((_pcidev)->func)
/* pciConfigPtr */
#define PCI_CFG_TAG(_pcidev) (((pciConfigPtr)(_pcidev)->thisCard)->tag)
#define PCI_CFG_BUS(_pcidev) (((pciConfigPtr)(_pcidev)->thisCard)->busnum)
#define PCI_CFG_DEV(_pcidev) (((pciConfigPtr)(_pcidev)->thisCard)->devnum)
#define PCI_CFG_FUNC(_pcidev) (((pciConfigPtr)(_pcidev)->thisCard)->funcnum)
/* region addr: xfree86 uses different fields for memory regions and I/O ports */
#define PCI_REGION_BASE(_pcidev, _b, _type) \
(((_type) == REGION_MEM) ? (_pcidev)->memBase[(_b)] \
: (_pcidev)->ioBase[(_b)])
/* region size: xfree86 uses the log2 of the region size,
* but with zero meaning no region, not size of one XXX */
#define PCI_REGION_SIZE(_pcidev, _b) \
(((_pcidev)->size[(_b)] > 0) ? (1 << (_pcidev)->size[(_b)]) : 0)
/* read/write PCI configuration space */
#define PCI_READ_BYTE(_pcidev, _value_ptr, _offset) \
*(_value_ptr) = pciReadByte(PCI_CFG_TAG(_pcidev), (_offset))
#define PCI_READ_LONG(_pcidev, _value_ptr, _offset) \
*(_value_ptr) = pciReadLong(PCI_CFG_TAG(_pcidev), (_offset))
#define PCI_WRITE_LONG(_pcidev, _value, _offset) \
pciWriteLong(PCI_CFG_TAG(_pcidev), (_offset), (_value))
#else /* XSERVER_LIBPCIACCESS */
typedef struct pci_device *pciVideoPtr;
#define PCI_DEV_VENDOR_ID(_pcidev) ((_pcidev)->vendor_id)
#define PCI_DEV_DEVICE_ID(_pcidev) ((_pcidev)->device_id)
#define PCI_DEV_REVISION(_pcidev) ((_pcidev)->revision)
#define PCI_SUB_VENDOR_ID(_pcidev) ((_pcidev)->subvendor_id)
#define PCI_SUB_DEVICE_ID(_pcidev) ((_pcidev)->subdevice_id)
/* pci-rework functions take a 'pci_device' parameter instead of a tag */
#define PCI_DEV_TAG(_pcidev) (_pcidev)
/* PCI_DEV macros, typically used in printf's, add domain ? XXX */
#define PCI_DEV_BUS(_pcidev) ((_pcidev)->bus)
#define PCI_DEV_DEV(_pcidev) ((_pcidev)->dev)
#define PCI_DEV_FUNC(_pcidev) ((_pcidev)->func)
/* pci-rework functions take a 'pci_device' parameter instead of a tag */
#define PCI_CFG_TAG(_pcidev) (_pcidev)
/* PCI_CFG macros, typically used in DRI init, contain the domain */
#define PCI_CFG_BUS(_pcidev) (((_pcidev)->domain << 8) | \
(_pcidev)->bus)
#define PCI_CFG_DEV(_pcidev) ((_pcidev)->dev)
#define PCI_CFG_FUNC(_pcidev) ((_pcidev)->func)
#define PCI_REGION_BASE(_pcidev, _b, _type) ((_pcidev)->regions[(_b)].base_addr)
#define PCI_REGION_SIZE(_pcidev, _b) ((_pcidev)->regions[(_b)].size)
#define PCI_READ_BYTE(_pcidev, _value_ptr, _offset) \
pci_device_cfg_read_u8((_pcidev), (_value_ptr), (_offset))
#define PCI_READ_LONG(_pcidev, _value_ptr, _offset) \
pci_device_cfg_read_u32((_pcidev), (_value_ptr), (_offset))
#define PCI_WRITE_LONG(_pcidev, _value, _offset) \
pci_device_cfg_write_u32((_pcidev), (_value), (_offset))
#endif /* XSERVER_LIBPCIACCESS */
#endif /* CIRPCIRENAME_H */

523
hw/xfree86/drivers/video/chips/src/ct_regs.c Normal file
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/*
* Created 1998 by David Bateman <dbateman@eng.uts.edu.au>
*
* Permission to use, copy, modify, distribute, and sell this software and its
* documentation for any purpose is hereby granted without fee, provided that
* the above copyright notice appear in all copies and that both that
* copyright notice and this permission notice appear in supporting
* documentation, and that the name of the authors not be used in
* advertising or publicity pertaining to distribution of the software without
* specific, written prior permission. The authors makes no representations
* about the suitability of this software for any purpose. It is provided
* "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
/*
* The functions in this file are used to read/write the C&T extension register
* and supply MMIO replacements of the VGA register access functions in
* vgaHW.c for chips that support MMIO access (eg 69000). Unlike the MGA
* chips, for instance, the C&T chipsets don't have a direct mapping between
* the MMIO mapped vga registers and the PIO versions.
*
* In General, these are the ONLY supported way of access the video processors
* registers. Exception are
*
* 1) chipsFindIsaDevice, where we don't know the chipset and so we don't know
* if the chipset supports MMIO access to its VGA registers, and we don't
* know the chips MemBase address and so can't map the VGA registers even
* if the chip did support MMIO. This effectively limits the use of non-PCI
* MMIO and multihead to a single card accessing 0x3D6/0x3D7. I.E. You can
* only have a single C&T card in a non-PCI multihead arrangement. Also as
* ISA has no method to disable I/O access to a card ISA multihead will
* never be supported.
*
* 2) ct_Blitter.h, ct_BlitMM.h and ct_BltHiQV.h, where speed is crucial and
* we know exactly whether we are using MMIO or PIO.
*
* 3) The 6554x 32bit DRxx in ct_cursor.c where the choice between MMIO and
* PIO is made explicitly
*/
/* All drivers should typically include these */
#include "xf86.h"
#include "xf86_OSproc.h"
/* Everything using inb/outb, etc needs "compiler.h" */
#include "compiler.h"
/* Drivers that need to access the PCI config space directly need this */
#include "xf86Pci.h"
/* Driver specific headers */
#include "ct_driver.h"
#define CHIPS_MONO_STAT_1 0x3BA
#define CHIPS_STAT_0 0x3BA
#define CHIPS_MSS 0x3CB
#define CHIPS_IOSS 0x3CD
#define CHIPS_FR_INDEX 0x3D0
#define CHIPS_FR_DATA 0x3D1
#define CHIPS_MR_INDEX 0x3D2
#define CHIPS_MR_DATA 0x3D3
#define CHIPS_XR_INDEX 0x3D6
#define CHIPS_XR_DATA 0x3D7
#define CHIPS_COLOR_STAT_1 0x3DA
#define CHIPS_MMIO_MONO_CRTC_INDEX 0x768
#define CHIPS_MMIO_MONO_CRTC_DATA 0x769
#define CHIPS_MMIO_MONO_STAT_1 0x774
#define CHIPS_MMIO_ATTR_INDEX 0x780
#define CHIPS_MMIO_ATTR_DATA_W 0x780
#define CHIPS_MMIO_ATTR_DATA_R 0x781
#define CHIPS_MMIO_STAT_0 0x784
#define CHIPS_MMIO_MISC_OUT_W 0x784
#define CHIPS_MMIO_SEQ_INDEX 0x788
#define CHIPS_MMIO_SEQ_DATA 0x789
#define CHIPS_MMIO_DAC_MASK 0x78C
#define CHIPS_MMIO_DAC_READ_ADDR 0x78D
#define CHIPS_MMIO_DAC_WRITE_ADDR 0x790
#define CHIPS_MMIO_DAC_DATA 0x791
#define CHIPS_MMIO_FEATURE_R 0x794
#define CHIPS_MMIO_MSS 0x795
#define CHIPS_MMIO_MISC_OUT_R 0x798
#define CHIPS_MMIO_IOSS 0x799
#define CHIPS_MMIO_GRAPH_INDEX 0x79C
#define CHIPS_MMIO_GRAPH_DATA 0x79D
#define CHIPS_MMIO_FR_INDEX 0x7A0
#define CHIPS_MMIO_FR_DATA 0x7A1
#define CHIPS_MMIO_MR_INDEX 0x7A4
#define CHIPS_MMIO_MR_DATA 0x7A5
#define CHIPS_MMIO_COLOR_CRTC_INDEX 0x7A8
#define CHIPS_MMIO_COLOR_CRTC_DATA 0x7A9
#define CHIPS_MMIO_XR_INDEX 0x7AC
#define CHIPS_MMIO_XR_DATA 0x7AD
#define CHIPS_MMIO_COLOR_STAT_1 0x7B4
/*
* PIO Access to the C&T extension registers
*/
static void
chipsStdWriteXR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
{
outb(cPtr->PIOBase + CHIPS_XR_INDEX, index);
outb(cPtr->PIOBase + CHIPS_XR_DATA, value);
}
static CARD8
chipsStdReadXR(CHIPSPtr cPtr, CARD8 index)
{
outb(cPtr->PIOBase + CHIPS_XR_INDEX, index);
return inb(cPtr->PIOBase + CHIPS_XR_DATA);
}
static void
chipsStdWriteFR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
{
outb(cPtr->PIOBase + CHIPS_FR_INDEX, index);
outb(cPtr->PIOBase + CHIPS_FR_DATA, value);
}
static CARD8
chipsStdReadFR(CHIPSPtr cPtr, CARD8 index)
{
outb(cPtr->PIOBase + CHIPS_FR_INDEX, index);
return inb(cPtr->PIOBase + CHIPS_FR_DATA);
}
static void
chipsStdWriteMR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
{
outb(cPtr->PIOBase + CHIPS_MR_INDEX, index);
outb(cPtr->PIOBase + CHIPS_MR_DATA, value);
}
static CARD8
chipsStdReadMR(CHIPSPtr cPtr, CARD8 index)
{
outb(cPtr->PIOBase + CHIPS_MR_INDEX, index);
return inb(cPtr->PIOBase + CHIPS_MR_DATA);
}
static void
chipsStdWriteMSS(CHIPSPtr cPtr, vgaHWPtr hwp, CARD8 value)
{
outb(cPtr->PIOBase + CHIPS_MSS, value);
}
static CARD8
chipsStdReadMSS(CHIPSPtr cPtr)
{
return inb(cPtr->PIOBase + CHIPS_MSS);
}
static void
chipsStdWriteIOSS(CHIPSPtr cPtr, CARD8 value)
{
outb(cPtr->PIOBase + CHIPS_IOSS, value);
}
static CARD8
chipsStdReadIOSS(CHIPSPtr cPtr)
{
return inb(cPtr->PIOBase + CHIPS_IOSS);
}
void
CHIPSSetStdExtFuncs(CHIPSPtr cPtr)
{
cPtr->writeFR = chipsStdWriteFR;
cPtr->readFR = chipsStdReadFR;
cPtr->writeMR = chipsStdWriteMR;
cPtr->readMR = chipsStdReadMR;
cPtr->writeXR = chipsStdWriteXR;
cPtr->readXR = chipsStdReadXR;
cPtr->writeMSS = chipsStdWriteMSS;
cPtr->readMSS = chipsStdReadMSS;
cPtr->writeIOSS = chipsStdWriteIOSS;
cPtr->readIOSS = chipsStdReadIOSS;
}
/*
* MMIO Access to the C&T extension registers
*/
#define chipsminb(p) MMIO_IN8(cPtr->MMIOBaseVGA, (p))
#define chipsmoutb(p,v) MMIO_OUT8(cPtr->MMIOBaseVGA, (p),(v))
static void
chipsMmioWriteXR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
{
chipsmoutb(CHIPS_MMIO_XR_INDEX, index);
chipsmoutb(CHIPS_MMIO_XR_DATA, value);
}
static CARD8
chipsMmioReadXR(CHIPSPtr cPtr, CARD8 index)
{
chipsmoutb(CHIPS_MMIO_XR_INDEX, index);
return chipsminb(CHIPS_MMIO_XR_DATA);
}
static void
chipsMmioWriteFR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
{
chipsmoutb(CHIPS_MMIO_FR_INDEX, index);
chipsmoutb(CHIPS_MMIO_FR_DATA, value);
}
static CARD8
chipsMmioReadFR(CHIPSPtr cPtr, CARD8 index)
{
chipsmoutb(CHIPS_MMIO_FR_INDEX, index);
return chipsminb(CHIPS_MMIO_FR_DATA);
}
static void
chipsMmioWriteMR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
{
chipsmoutb(CHIPS_MMIO_MR_INDEX, index);
chipsmoutb(CHIPS_MMIO_MR_DATA, value);
}
static CARD8
chipsMmioReadMR(CHIPSPtr cPtr, CARD8 index)
{
chipsmoutb(CHIPS_MMIO_MR_INDEX, index);
return chipsminb(CHIPS_MMIO_MR_DATA);
}
static void
chipsMmioWriteMSS(CHIPSPtr cPtr, vgaHWPtr hwp, CARD8 value)
{
/* 69030 MMIO Fix.
*
* <value> determines which MMIOBase to use; either
* Pipe A or Pipe B. -GHB
*/
if ((value & MSS_SHADOW) == MSS_PIPE_B)
cPtr->MMIOBaseVGA = cPtr->MMIOBasePipeB;
else
cPtr->MMIOBaseVGA = cPtr->MMIOBasePipeA;
hwp->MMIOBase = cPtr->MMIOBaseVGA;
/* Since our Pipe constants don't set bit 3 of MSS, the value
* written here has no effect on the hardware's behavior. It
* does allow us to use the value returned by readMSS() to key
* the above logic, though. -GHB
*/
chipsmoutb(CHIPS_MMIO_MSS, value);
}
static CARD8
chipsMmioReadMSS(CHIPSPtr cPtr)
{
return chipsminb(CHIPS_MMIO_MSS);
}
static void
chipsMmioWriteIOSS(CHIPSPtr cPtr, CARD8 value)
{
chipsmoutb(CHIPS_MMIO_IOSS, value);
}
static CARD8
chipsMmioReadIOSS(CHIPSPtr cPtr)
{
return chipsminb(CHIPS_MMIO_IOSS);
}
void
CHIPSSetMmioExtFuncs(CHIPSPtr cPtr)
{
cPtr->writeFR = chipsMmioWriteFR;
cPtr->readFR = chipsMmioReadFR;
cPtr->writeMR = chipsMmioWriteMR;
cPtr->readMR = chipsMmioReadMR;
cPtr->writeXR = chipsMmioWriteXR;
cPtr->readXR = chipsMmioReadXR;
cPtr->writeMSS = chipsMmioWriteMSS;
cPtr->readMSS = chipsMmioReadMSS;
cPtr->writeIOSS = chipsMmioWriteIOSS;
cPtr->readIOSS = chipsMmioReadIOSS;
}
/*
* MMIO versions of the VGA register access functions.
*/
#define minb(p) MMIO_IN8(hwp->MMIOBase, (p))
#define moutb(p,v) MMIO_OUT8(hwp->MMIOBase, (p),(v))
static void
chipsMmioWriteCrtc(vgaHWPtr hwp, CARD8 index, CARD8 value)
{
if (hwp->IOBase == VGA_IOBASE_MONO) {
moutb(CHIPS_MMIO_MONO_CRTC_INDEX, index);
moutb(CHIPS_MMIO_MONO_CRTC_DATA, value);
} else {
moutb(CHIPS_MMIO_COLOR_CRTC_INDEX, index);
moutb(CHIPS_MMIO_COLOR_CRTC_DATA, value);
}
}
static CARD8
chipsMmioReadCrtc(vgaHWPtr hwp, CARD8 index)
{
if (hwp->IOBase == VGA_IOBASE_MONO) {
moutb(CHIPS_MMIO_MONO_CRTC_INDEX, index);
return minb(CHIPS_MMIO_MONO_CRTC_DATA);
} else {
moutb(CHIPS_MMIO_COLOR_CRTC_INDEX, index);
return minb(CHIPS_MMIO_COLOR_CRTC_DATA);
}
}
static void
chipsMmioWriteGr(vgaHWPtr hwp, CARD8 index, CARD8 value)
{
moutb(CHIPS_MMIO_GRAPH_INDEX, index);
moutb(CHIPS_MMIO_GRAPH_DATA, value);
}
static CARD8
chipsMmioReadGr(vgaHWPtr hwp, CARD8 index)
{
moutb(CHIPS_MMIO_GRAPH_INDEX, index);
return minb(CHIPS_MMIO_GRAPH_DATA);
}
static void
chipsMmioWriteSeq(vgaHWPtr hwp, CARD8 index, CARD8 value)
{
moutb(CHIPS_MMIO_SEQ_INDEX, index);
moutb(CHIPS_MMIO_SEQ_DATA, value);
}
static CARD8
chipsMmioReadSeq(vgaHWPtr hwp, CARD8 index)
{
moutb(CHIPS_MMIO_SEQ_INDEX, index);
return minb(CHIPS_MMIO_SEQ_DATA);
}
static void
chipsMmioWriteAttr(vgaHWPtr hwp, CARD8 index, CARD8 value)
{
if (hwp->paletteEnabled)
index &= ~0x20;
else
index |= 0x20;
if (hwp->IOBase == VGA_IOBASE_MONO)
(void) minb(CHIPS_MMIO_MONO_STAT_1);
else
(void) minb(CHIPS_MMIO_COLOR_STAT_1);
moutb(CHIPS_MMIO_ATTR_INDEX, index);
moutb(CHIPS_MMIO_ATTR_DATA_W, value);
}
static CARD8
chipsMmioReadAttr(vgaHWPtr hwp, CARD8 index)
{
if (hwp->paletteEnabled)
index &= ~0x20;
else
index |= 0x20;
if (hwp->IOBase == VGA_IOBASE_MONO)
(void) minb(CHIPS_MMIO_MONO_STAT_1);
else
(void) minb(CHIPS_MMIO_COLOR_STAT_1);
moutb(CHIPS_MMIO_ATTR_INDEX, index);
return minb(CHIPS_MMIO_ATTR_DATA_R);
}
static void
chipsMmioWriteMiscOut(vgaHWPtr hwp, CARD8 value)
{
moutb(CHIPS_MMIO_MISC_OUT_W, value);
}
static CARD8
chipsMmioReadMiscOut(vgaHWPtr hwp)
{
return minb(CHIPS_MMIO_MISC_OUT_R);
}
static void
chipsMmioEnablePalette(vgaHWPtr hwp)
{
if (hwp->IOBase == VGA_IOBASE_MONO)
(void) minb(CHIPS_MMIO_MONO_STAT_1);
else
(void) minb(CHIPS_MMIO_COLOR_STAT_1);
moutb(CHIPS_MMIO_ATTR_INDEX, 0x00);
hwp->paletteEnabled = TRUE;
}
static void
chipsMmioDisablePalette(vgaHWPtr hwp)
{
if (hwp->IOBase == VGA_IOBASE_MONO)
(void) minb(CHIPS_MMIO_MONO_STAT_1);
else
(void) minb(CHIPS_MMIO_COLOR_STAT_1);
moutb(CHIPS_MMIO_ATTR_INDEX, 0x20);
hwp->paletteEnabled = FALSE;
}
static void
chipsMmioWriteDacMask(vgaHWPtr hwp, CARD8 value)
{
moutb(CHIPS_MMIO_DAC_MASK, value);
}
static CARD8
chipsMmioReadDacMask(vgaHWPtr hwp)
{
return minb(CHIPS_MMIO_DAC_MASK);
}
static void
chipsMmioWriteDacReadAddr(vgaHWPtr hwp, CARD8 value)
{
moutb(CHIPS_MMIO_DAC_READ_ADDR, value);
}
static void
chipsMmioWriteDacWriteAddr(vgaHWPtr hwp, CARD8 value)
{
moutb(CHIPS_MMIO_DAC_WRITE_ADDR, value);
}
static void
chipsMmioWriteDacData(vgaHWPtr hwp, CARD8 value)
{
moutb(CHIPS_MMIO_DAC_DATA, value);
}
static CARD8
chipsMmioReadDacData(vgaHWPtr hwp)
{
return minb(CHIPS_MMIO_DAC_DATA);
}
static CARD8
chipsMmioReadST00(vgaHWPtr hwp)
{
return minb(CHIPS_MMIO_STAT_0);
}
static CARD8
chipsMmioReadST01(vgaHWPtr hwp)
{
if (hwp->IOBase == VGA_IOBASE_MONO)
return minb(CHIPS_MMIO_MONO_STAT_1);
else
return minb(CHIPS_MMIO_COLOR_STAT_1);
}
static CARD8
chipsMmioReadFCR(vgaHWPtr hwp)
{
return minb(CHIPS_MMIO_FEATURE_R);
}
static void
chipsMmioWriteFCR(vgaHWPtr hwp, CARD8 value)
{
if (hwp->IOBase == VGA_IOBASE_MONO) {
moutb(CHIPS_MMIO_MONO_STAT_1, value);
} else {
moutb(CHIPS_MMIO_COLOR_STAT_1, value);
}
}
void
CHIPSHWSetMmioFuncs(ScrnInfoPtr pScrn, CARD8 *base, int offset)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
hwp->writeCrtc = chipsMmioWriteCrtc;
hwp->readCrtc = chipsMmioReadCrtc;
hwp->writeGr = chipsMmioWriteGr;
hwp->readGr = chipsMmioReadGr;
hwp->writeAttr = chipsMmioWriteAttr;
hwp->readAttr = chipsMmioReadAttr;
hwp->writeSeq = chipsMmioWriteSeq;
hwp->readSeq = chipsMmioReadSeq;
hwp->writeMiscOut = chipsMmioWriteMiscOut;
hwp->readMiscOut = chipsMmioReadMiscOut;
hwp->enablePalette = chipsMmioEnablePalette;
hwp->disablePalette = chipsMmioDisablePalette;
hwp->writeDacMask = chipsMmioWriteDacMask;
hwp->readDacMask = chipsMmioReadDacMask;
hwp->writeDacWriteAddr = chipsMmioWriteDacWriteAddr;
hwp->writeDacReadAddr = chipsMmioWriteDacReadAddr;
hwp->writeDacData = chipsMmioWriteDacData;
hwp->readDacData = chipsMmioReadDacData;
hwp->readST00 = chipsMmioReadST00;
hwp->readST01 = chipsMmioReadST01;
hwp->readFCR = chipsMmioReadFCR;
hwp->writeFCR = chipsMmioWriteFCR;
hwp->MMIOBase = base;
hwp->MMIOOffset = offset;
}

243
hw/xfree86/drivers/video/chips/src/ct_shadow.c Normal file
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#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86.h"
#include "xf86_OSproc.h"
#include "xf86Pci.h"
#include "shadowfb.h"
#include "servermd.h"
#include "ct_driver.h"
void
chipsRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
int width, height, Bpp, FBPitch;
unsigned char *src, *dst;
Bpp = pScrn->bitsPerPixel >> 3;
FBPitch = BitmapBytePad(pScrn->displayWidth * pScrn->bitsPerPixel);
while(num--) {
width = (pbox->x2 - pbox->x1) * Bpp;
height = pbox->y2 - pbox->y1;
src = cPtr->ShadowPtr + (pbox->y1 * cPtr->ShadowPitch) +
(pbox->x1 * Bpp);
dst = cPtr->FbBase + (pbox->y1 * FBPitch) + (pbox->x1 * Bpp);
while(height--) {
memcpy(dst, src, width);
dst += FBPitch;
src += cPtr->ShadowPitch;
}
pbox++;
}
}
void
chipsPointerMoved(SCRN_ARG_TYPE arg, int x, int y)
{
SCRN_INFO_PTR(arg);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
int newX, newY;
if(cPtr->Rotate == 1) {
newX = pScrn->pScreen->height - y - 1;
newY = x;
} else {
newX = y;
newY = pScrn->pScreen->width - x - 1;
}
(*cPtr->PointerMoved)(arg, newX, newY);
}
void
chipsRefreshArea8(ScrnInfoPtr pScrn, int num, BoxPtr pbox)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
int count, width, height, y1, y2, dstPitch, srcPitch;
CARD8 *dstPtr, *srcPtr, *src;
CARD32 *dst;
dstPitch = pScrn->displayWidth;
srcPitch = -cPtr->Rotate * cPtr->ShadowPitch;
while(num--) {
width = pbox->x2 - pbox->x1;
y1 = pbox->y1 & ~3;
y2 = (pbox->y2 + 3) & ~3;
height = (y2 - y1) >> 2; /* in dwords */
if(cPtr->Rotate == 1) {
dstPtr = cPtr->FbBase +
(pbox->x1 * dstPitch) + pScrn->virtualX - y2;
srcPtr = cPtr->ShadowPtr + ((1 - y2) * srcPitch) + pbox->x1;
} else {
dstPtr = cPtr->FbBase +
((pScrn->virtualY - pbox->x2) * dstPitch) + y1;
srcPtr = cPtr->ShadowPtr + (y1 * srcPitch) + pbox->x2 - 1;
}
while(width--) {
src = srcPtr;
dst = (CARD32*)dstPtr;
count = height;
while(count--) {
*(dst++) = src[0] | (src[srcPitch] << 8) |
(src[srcPitch * 2] << 16) |
(src[srcPitch * 3] << 24);
src += srcPitch * 4;
}
srcPtr += cPtr->Rotate;
dstPtr += dstPitch;
}
pbox++;
}
}
void
chipsRefreshArea16(ScrnInfoPtr pScrn, int num, BoxPtr pbox)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
int count, width, height, y1, y2, dstPitch, srcPitch;
CARD16 *dstPtr, *srcPtr, *src;
CARD32 *dst;
dstPitch = pScrn->displayWidth;
srcPitch = -cPtr->Rotate * cPtr->ShadowPitch >> 1;
while(num--) {
width = pbox->x2 - pbox->x1;
y1 = pbox->y1 & ~1;
y2 = (pbox->y2 + 1) & ~1;
height = (y2 - y1) >> 1; /* in dwords */
if(cPtr->Rotate == 1) {
dstPtr = (CARD16*)cPtr->FbBase +
(pbox->x1 * dstPitch) + pScrn->virtualX - y2;
srcPtr = (CARD16*)cPtr->ShadowPtr +
((1 - y2) * srcPitch) + pbox->x1;
} else {
dstPtr = (CARD16*)cPtr->FbBase +
((pScrn->virtualY - pbox->x2) * dstPitch) + y1;
srcPtr = (CARD16*)cPtr->ShadowPtr +
(y1 * srcPitch) + pbox->x2 - 1;
/* ErrorF("dst: %x base: %x\n",dstPtr,cPtr->FbBase);*/
}
while(width--) {
src = srcPtr;
dst = (CARD32*)dstPtr;
count = height;
while(count--) {
*(dst++) = src[0] | (src[srcPitch] << 16);
src += srcPitch * 2;
}
srcPtr += cPtr->Rotate;
dstPtr += dstPitch;
}
pbox++;
}
}
/* this one could be faster */
void
chipsRefreshArea24(ScrnInfoPtr pScrn, int num, BoxPtr pbox)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
int count, width, height, y1, y2, dstPitch, srcPitch;
CARD8 *dstPtr, *srcPtr, *src;
CARD32 *dst;
dstPitch = BitmapBytePad(pScrn->displayWidth * 24);
srcPitch = -cPtr->Rotate * cPtr->ShadowPitch;
while(num--) {
width = pbox->x2 - pbox->x1;
y1 = pbox->y1 & ~3;
y2 = (pbox->y2 + 3) & ~3;
height = (y2 - y1) >> 2; /* blocks of 3 dwords */
if(cPtr->Rotate == 1) {
dstPtr = cPtr->FbBase +
(pbox->x1 * dstPitch) + ((pScrn->virtualX - y2) * 3);
srcPtr = cPtr->ShadowPtr + ((1 - y2) * srcPitch) + (pbox->x1 * 3);
} else {
dstPtr = cPtr->FbBase +
((pScrn->virtualY - pbox->x2) * dstPitch) + (y1 * 3);
srcPtr = cPtr->ShadowPtr + (y1 * srcPitch) + (pbox->x2 * 3) - 3;
}
while(width--) {
src = srcPtr;
dst = (CARD32*)dstPtr;
count = height;
while(count--) {
dst[0] = src[0] | (src[1] << 8) | (src[2] << 16) |
(src[srcPitch] << 24);
dst[1] = src[srcPitch + 1] | (src[srcPitch + 2] << 8) |
(src[srcPitch * 2] << 16) |
(src[(srcPitch * 2) + 1] << 24);
dst[2] = src[(srcPitch * 2) + 2] | (src[srcPitch * 3] << 8) |
(src[(srcPitch * 3) + 1] << 16) |
(src[(srcPitch * 3) + 2] << 24);
dst += 3;
src += srcPitch * 4;
}
srcPtr += cPtr->Rotate * 3;
dstPtr += dstPitch;
}
pbox++;
}
}
void
chipsRefreshArea32(ScrnInfoPtr pScrn, int num, BoxPtr pbox)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
int count, width, height, dstPitch, srcPitch;
CARD32 *dstPtr, *srcPtr, *src, *dst;
dstPitch = pScrn->displayWidth;
srcPitch = -cPtr->Rotate * cPtr->ShadowPitch >> 2;
while(num--) {
width = pbox->x2 - pbox->x1;
height = pbox->y2 - pbox->y1;
if(cPtr->Rotate == 1) {
dstPtr = (CARD32*)cPtr->FbBase +
(pbox->x1 * dstPitch) + pScrn->virtualX - pbox->y2;
srcPtr = (CARD32*)cPtr->ShadowPtr +
((1 - pbox->y2) * srcPitch) + pbox->x1;
} else {
dstPtr = (CARD32*)cPtr->FbBase +
((pScrn->virtualY - pbox->x2) * dstPitch) + pbox->y1;
srcPtr = (CARD32*)cPtr->ShadowPtr +
(pbox->y1 * srcPitch) + pbox->x2 - 1;
}
while(width--) {
src = srcPtr;
dst = dstPtr;
count = height;
while(count--) {
*(dst++) = *src;
src += srcPitch;
}
srcPtr += cPtr->Rotate;
dstPtr += dstPitch;
}
pbox++;
}
}

1033
hw/xfree86/drivers/video/chips/src/ct_video.c Normal file
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File diff suppressed because it is too large Load Diff

338
hw/xfree86/drivers/video/chips/util/AsmMacros.h Normal file
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/*
* (c) Copyright 1993,1994 by David Wexelblat <dwex@xfree86.org>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* DAVID WEXELBLAT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of David Wexelblat shall not be
* used in advertising or otherwise to promote the sale, use or other dealings
* in this Software without prior written authorization from David Wexelblat.
*
*/
/*
* Copyright 1997
* Digital Equipment Corporation. All rights reserved.
* This software is furnished under license and may be used and copied only in
* accordance with the following terms and conditions. Subject to these
* conditions, you may download, copy, install, use, modify and distribute
* this software in source and/or binary form. No title or ownership is
* transferred hereby.
*
* 1) Any source code used, modified or distributed must reproduce and retain
* this copyright notice and list of conditions as they appear in the source
* file.
*
* 2) No right is granted to use any trade name, trademark, or logo of Digital
* Equipment Corporation. Neither the "Digital Equipment Corporation" name
* nor any trademark or logo of Digital Equipment Corporation may be used
* to endorse or promote products derived from this software without the
* prior written permission of Digital Equipment Corporation.
*
* 3) This software is provided "AS-IS" and any express or implied warranties,
* including but not limited to, any implied warranties of merchantability,
* fitness for a particular purpose, or non-infringement are disclaimed. In
* no event shall DIGITAL be liable for any damages whatsoever, and in
* particular, DIGITAL shall not be liable for special, indirect,
* consequential, or incidental damages or damages for
* lost profits, loss of revenue or loss of use, whether such damages arise
* in contract,
* negligence, tort, under statute, in equity, at law or otherwise, even if
* advised of the possibility of such damage.
*
*/
#if defined(__GNUC__)
#if defined(linux) && (defined(__alpha__) || defined(__ia64__))
#undef inb
#undef inw
#undef inl
#undef outb
#undef outw
#undef outl
#define inb _inb
#define inw _inw
#define inl _inl
#define outb(p,v) _outb((v),(p))
#define outw(p,v) _outw((v),(p))
#define outl(p,v) _outl((v),(p))
#else
#if defined(__sparc__)
#ifndef ASI_PL
#define ASI_PL 0x88
#endif
static __inline__ void
outb(unsigned long port, char val)
{
__asm__ __volatile__("stba %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL));
}
static __inline__ void
outw(unsigned long port, char val)
{
__asm__ __volatile__("stha %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL));
}
static __inline__ void
outl(unsigned long port, char val)
{
__asm__ __volatile__("sta %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL));
}
static __inline__ unsigned int
inb(unsigned long port)
{
unsigned char ret;
__asm__ __volatile__("lduba [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL));
return ret;
}
static __inline__ unsigned int
inw(unsigned long port)
{
unsigned char ret;
__asm__ __volatile__("lduha [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL));
return ret;
}
static __inline__ unsigned int
inl(unsigned long port)
{
unsigned char ret;
__asm__ __volatile__("lda [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL));
return ret;
}
#else
#ifdef __arm32__
unsigned int IOPortBase; /* Memory mapped I/O port area */
static __inline__ void
outb(short port, char val)
{
if ((unsigned short)port >= 0x400) return;
*(volatile unsigned char*)(((unsigned short)(port))+IOPortBase) = val;
}
static __inline__ void
outw(short port, short val)
{
if ((unsigned short)port >= 0x400) return;
*(volatile unsigned short*)(((unsigned short)(port))+IOPortBase) = val;
}
static __inline__ void
outl(short port, int val)
{
if ((unsigned short)port >= 0x400) return;
*(volatile unsigned long*)(((unsigned short)(port))+IOPortBase) = val;
}
static __inline__ unsigned int
inb(short port)
{
if ((unsigned short)port >= 0x400) return((unsigned int)-1);
return(*(volatile unsigned char*)(((unsigned short)(port))+IOPortBase));
}
static __inline__ unsigned int
inw(short port)
{
if ((unsigned short)port >= 0x400) return((unsigned int)-1);
return(*(volatile unsigned short*)(((unsigned short)(port))+IOPortBase));
}
static __inline__ unsigned int
inl(short port)
{
if ((unsigned short)port >= 0x400) return((unsigned int)-1);
return(*(volatile unsigned long*)(((unsigned short)(port))+IOPortBase));
}
#else /* __arm32__ */
#if defined(__FreeBSD__) && defined(__alpha__)
#include <sys/types.h>
extern void outb(u_int32_t port, u_int8_t val);
extern void outw(u_int32_t port, u_int16_t val);
extern void outl(u_int32_t port, u_int32_t val);
extern u_int8_t inb(u_int32_t port);
extern u_int16_t inw(u_int32_t port);
extern u_int32_t inl(u_int32_t port);
#else
#ifdef GCCUSESGAS
static __inline__ void
outb(short port, char val)
{
__asm__ __volatile__("outb %0,%1" : :"a" (val), "d" (port));
}
static __inline__ void
outw(short portm, short val)
{
__asm__ __volatile__("outw %0,%1" : :"a" (val), "d" (port));
}
static __inline__ void
outl(short port, unsigned int val)
{
__asm__ __volatile__("outl %0,%1" : :"a" (val), "d" (port));
}
static __inline__ unsigned int
inb(short port)
{
unsigned char ret;
__asm__ __volatile__("inb %1,%0" :
"=a" (ret) :
"d" (port));
return ret;
}
static __inline__ unsigned int
inw(short port)
{
unsigned short ret;
__asm__ __volatile__("inw %1,%0" :
"=a" (ret) :
"d" (port));
return ret;
}
static __inline__ unsigned int
inl(short port)
{
unsigned int ret;
__asm__ __volatile__("inl %1,%0" :
"=a" (ret) :
"d" (port));
return ret;
}
#else /* GCCUSESGAS */
static __inline__ void
outb(short port, char val)
{
__asm__ __volatile__("out%B0 (%1)" : :"a" (val), "d" (port));
}
static __inline__ void
outw(short port, short val)
{
__asm__ __volatile__("out%W0 (%1)" : :"a" (val), "d" (port));
}
static __inline__ void
outl(short port, unsigned int val)
{
__asm__ __volatile__("out%L0 (%1)" : :"a" (val), "d" (port));
}
static __inline__ unsigned int
inb(short port)
{
unsigned int ret;
__asm__ __volatile__("in%B0 (%1)" :
"=a" (ret) :
"d" (port));
return ret;
}
static __inline__ unsigned int
inw(short port)
{
unsigned int ret;
__asm__ __volatile__("in%W0 (%1)" :
"=a" (ret) :
"d" (port));
return ret;
}
static __inline__ unsigned int
inl(short port)
{
unsigned int ret;
__asm__ __volatile__("in%L0 (%1)" :
"=a" (ret) :
"d" (port));
return ret;
}
#endif /* GCCUSESGAS */
#endif /* arm32 */
#endif /* linux && __sparc__ */
#endif /* linux && __alpha__ */
#endif /* __FreeBSD__ && __alpha__ */
#if defined(linux) || defined(__arm32__)
#define intr_disable()
#define intr_enable()
#else
static __inline__ void
intr_disable(void)
{
__asm__ __volatile__("cli");
}
static __inline__ void
intr_enable(void)
{
__asm__ __volatile__("sti");
}
#endif /* else !linux && !__arm32__ */
#else /* __GNUC__ */
#if defined(_MINIX) && defined(_ACK)
/* inb, outb, inw and outw are defined in the library */
/* ... but I've no idea if the same is true for inl & outl */
u8_t inb(U16_t);
void outb(U16_t, U8_t);
u16_t inw(U16_t);
void outw(U16_t, U16_t);
u32_t inl(U16_t);
void outl(U16_t, U32_t);
#else /* not _MINIX and _ACK */
# if defined(__STDC__) && (__STDC__ == 1)
# define asm __asm
# endif
# ifdef SVR4
# include <sys/types.h>
# endif
# include <sys/inline.h>
# define intr_disable() asm("cli")
# define intr_enable() asm("sti")
#endif /* _MINIX and _ACK */
#endif /* __GNUC__ */

248
hw/xfree86/drivers/video/chips/util/dRegs.c Normal file
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#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include "iopl.h"
int main(void)
{
int i, HTotal, HDisplay, HSyncStart, HSyncEnd,
VTotal, VDisplay, VSyncStart, VSyncEnd;
unsigned char storeReg, bpp, shift, IOSS = 0, MSS = 0, again = 0;
unsigned short port;
int isHiQV = 0;
int is69030 = 0;
SET_IOPL();
printf("0x3C6\t0x%X\n",inw(0x3C6));
/* Check to see if the Chip is HiQV */
outb(0x3D6,0x02);
storeReg = inb(0x3D7);
if (storeReg == 0xE0 /* CT65550 */
|| storeReg == 0xE4 /* CT65554 */
|| storeReg == 0xE5 /* CT65555 */
|| storeReg == 0xF4 /* CT68554 */
|| storeReg == 0xC0) /* CT69000 */
{
isHiQV = 1;
} else if (storeReg == 0x30) {
outb(0x3D6,0x03);
storeReg = inb(0x3D7);
if (storeReg == 0xC) {
isHiQV = 1;
is69030 = 1;
IOSS=inb(0x3CD);
MSS=inb(0x3CB);
outb(0x3CD,((IOSS&0xE0)| 0x11)); /* Select Channel 0 */
outb(0x3CB,((MSS&0xF0)| 0x8));
again = 1;
printf("Pipeline A:\n");
}
}
again:
printf("port 0x3D6 (C&T)\n");
storeReg = inb(0x3D6);
shift = 3;
if (isHiQV==1) {
outw(0x102,1); /*global enable, VGA awake*/
printf("0x%2.2X\n",inb(0x3C3)&0xFF);
outb(0x3C3,0); /*disable VGA*/
outb(0x3C3,1); /*enable VGA*/
for(i = 0;i < 0xFF;i++){
outb(0x3D6,i);
printf("XR 0x%2.2X\t0x%2.2X\n",i,inb(0x3D7)&0xFF);
}
outb(0x3D6,0xE2);
bpp = inb(0x3D7)&0xF0;
} else {
outb(0x3D6, 0x70);
outw(0x3D6, (inw(0x3D6) | 0x8070));
outw(0x46E8,0x0016); /*setup mode*/
outw(0x102,1); /*global enable, VGA awake*/
outw(0x46E8,0x000E); /*exit from setup mode*/
printf("0x%2.2X\n",inb(0x3C3)&0xFF);
outb(0x3C3,0); /*disable VGA*/
outw(0x46E8,0x0000); /*exit from setup mode*/
outw(0x46E8,0x000E); /*exit from setup mode*/
outb(0x3C3,1); /*enable VGA*/
outw(0x46E8,0x0000); /*exit from setup mode*/
for(i = 0;i < 0x80;i++){
outb(0x3D6,i);
printf("XR 0x%2.2X\t0x%2.2X\n",i,inb(0x3D7)&0xFF);
}
outb(0x3D6,0x2B);
bpp = inb(0x3D7)&0xF0;
}
switch(bpp){
case 0x20:
bpp = 4;
break;
case 0x30:
bpp = 8;
break;
case 0x40:
bpp = 16;
shift = 2;
break;
case 0x50:
bpp = 24;
break;
default:
bpp = 0;
}
outb(0x3D6,storeReg);
printf("\nport 0x3D4 (CRTC)\n");
storeReg = inb(0x3D4);
if (isHiQV==1) {
for(i = 0;i < 0x7F;i++){
outb(0x3D4,i);
printf("CR 0x%2.2X\t0x%2.2X\n",i,inb(0x3D5)&0xFF);
}
outb(0x3D4,storeReg);
printf("\nport 0x3D0 (Flat Panel)\n");
storeReg = inb(0x3D0);
for(i = 0;i < 0x7F;i++){
outb(0x3D0,i);
printf("FR 0x%2.2X\t0x%2.2X\n",i,inb(0x3D1)&0xFF);
}
outb(0x3D1,storeReg);
printf("\nport 0x3D2 (Multimedia)\n");
storeReg = inb(0x3D2);
for(i = 0;i < 0x7F;i++){
outb(0x3D2,i);
printf("MR 0x%2.2X\t0x%2.2X\n",i,inb(0x3D3)&0xFF);
}
outb(0x3D3,storeReg);
} else {
for(i = 0;i < 0x40;i++){
outb(0x3D4,i);
printf("CR 0x%2.2X\t0x%2.2X\n",i,inb(0x3D5)&0xFF);
}
outb(0x3D4,storeReg);
}
printf("port 0x3CE (GC)\n");
storeReg = inb(0x3CE);
for(i = 0;i < 0x10;i++){
outb(0x3CE,i);
printf("GC 0x%2.2X\t0x%2.2X\n",i,inb(0x3CF)&0xFF);
}
outb(0x3CE,storeReg);
printf("port 0x3C4 (Sequencer)\n");
storeReg = inb(0x3C4);
for(i = 0;i < 0x10;i++){
outb(0x3C4,i);
printf("SQ 0x%2.2X\t0x%X2.2\n",i,inb(0x3C5)&0xFF);
}
outb(0x3C4,storeReg);
printf("port 0x3C0 (Attribute)\n");
inb(0x3DA);
storeReg = inb(0x3C0);
for(i = 0;i < 0xFF;i++){
inb(0x3DA);
outb(0x3C0,i);
printf("AT 0x%2.2X\t0x%2.2X\n",i,inb(0x3C1)&0xFF);
}
inb(0x3DA);
outb(0x3C0,storeReg);
printf("0x3CC\t0x%X\n",inb(0x3CC)&0xFF);
printf("0x3C2\t0x%X\n",inb(0x3C2)&0xFF);
printf("0x3C3\t0x%X\n",inb(0x3C2)&0xFF);
printf("0x3CA\t0x%X\n",inb(0x3CA)&0xFF);
printf("0x3DA\t0x%X\n",inb(0x3DA)&0xFF);
printf("\nRAMDAC\nport\tvalue\n");
for(port = 0x83C6; port < 0x83CA;port++){
printf("0x%4X\t0x%4X\n",port,inw(port));
}
if (isHiQV!=1) {
printf("\nBitBLT\nport\tvalue\n");
for(port = 0x83D0; port <= 0x9FD0;port+=0x400){
printf("0x%4.4X\t0x%4X\n",port,inw(port));
}
printf("\nH/W cursor\nport\tvalue\n");
for(port = 0xA3D0; port <= 0xB3D0;port+=0x400){
printf("0x%4.4X\t0x%4X\n",port,inw(port));
}
outb(0x3D6, 0x70);
outw(0x3D6, (inw(0x3D6) | 0x8070));
printf("0x46E8\t0x%8X\n",inl(0x46E8));
printf("0x4AE8\t0x%8X\n",inl(0x4AE8));
printf("0x102\t0x%8X\n",inl(0x102));
printf("0x103\t0x%8X\n",inl(0x103));
}
storeReg = inb(0x3D4);
{
outb(0x3D4,0);
HTotal = ((inb(0x3D5)&0xFF) + 5) << shift;
outb(0x3D4,1);
HDisplay = ((inb(0x3D5)&0xFF) + 1) << shift;
outb(0x3D4,4);
HSyncStart = ((inb(0x3D5)&0xFF) + 1) << shift;
outb(0x3D4,5);
HSyncEnd = inb(0x3D5)&0x1F;
outb(0x3D4,5);
HSyncEnd += HSyncStart >> shift;
HSyncEnd <<= shift;
outb(0x3D4,6);
VTotal = inb(0x3D5)&0xFF;
outb(0x3D4,7);
VTotal |= (inb(0x3D5)&0x1) << 8;
VTotal |= (inb(0x3D5)&0x20) << 4;
VTotal += 2;
VDisplay = (inb(0x3D5)&0x2) << 7;
VDisplay |= (inb(0x3D5)&0x40) << 3;
VSyncStart = (inb(0x3D5)&0x4) << 6;
VSyncStart |= (inb(0x3D5)&0x80) << 2;
outb(0x3D4,0x12);
VDisplay |= inb(0x3D5)&0xFF;
VDisplay += 1;
outb(0x3D4,0x10);
VSyncStart |= inb(0x3D5)&0xFF;
outb(0x3D4,0x11);
VSyncEnd = inb(0x3D5)&0xF;
VSyncEnd += VSyncStart;
}
outb(0x3D4,storeReg);
printf("\nModeLine with port 0x3D4 (CRTC) %d %d %d %d %d %d %d %d\n",
HDisplay, HSyncStart, HSyncEnd, HTotal,
VDisplay, VSyncStart, VSyncEnd, VTotal);
if (is69030==1) {
if (again==1) {
again=0;
printf("\n\nPipeline B:\n");
outb(0x3CD,((IOSS&0xE0)| 0x1F)); /* Select Channel 1 */
outb(0x3CB,((MSS&0xF0)| 0xF));
goto again;
} else {
outb(0x3CD,IOSS);
outb(0x3CB,MSS);
printf("\n\n0x3CB\t0x%X (MSS)\n",inb(0x3CB)&0xFF);
printf("0x3CD\t0x%X (IOSS)\n",inb(0x3CD)&0xFF);
}
}
RESET_IOPL();
return 0;
}

46
hw/xfree86/drivers/video/chips/util/iopl.h Normal file
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@@ -0,0 +1,46 @@
#ifdef __NetBSD__
# include <sys/types.h>
# include <machine/pio.h>
# include <machine/sysarch.h>
#else
# if defined(__linux__)
/* Can't because <sys/iopl.h> provides conflicting inb, outb, etc
* # include <sys/io.h>
*/
int iopl(int level);
# endif
# if defined(SVR4) && defined(i386) && defined(sun)
# include <sys/types.h>
# include <sys/sysi86.h>
# include <sys/v86.h>
# include <sys/psw.h>
# endif
# include "AsmMacros.h"
#endif /* NetBSD */
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#ifdef __NetBSD__
# define SET_IOPL() i386_iopl(3)
# define RESET_IOPL() i386_iopl(0)
#else
# if defined(SVR4) && defined(i386)
# ifndef SI86IOPL
# define SET_IOPL() sysi86(SI86V86,V86SC_IOPL,PS_IOPL)
# define RESET_IOPL() sysi86(SI86V86,V86SC_IOPL,0)
# else
# define SET_IOPL() sysi86(SI86IOPL,3)
# define RESET_IOPL() sysi86(SI86IOPL,0)
# endif
# else
# ifdef linux
# define SET_IOPL() iopl(3)
# define RESET_IOPL() iopl(0)
# else
# define SET_IOPL() (void)0
# define RESET_IOPL() (void)0
# endif
# endif
#endif

129
hw/xfree86/drivers/video/chips/util/mRegs.c Normal file
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#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include "iopl.h"
int hex2int(char* str);
int main(int argc, char** argv)
{
int i, value, index = 0;
char c, cport;
char* str;
unsigned int port, port1 = 0;
int query = 0;
if(argc < 2) {
printf("usage: %s [Cvvxx [Cvvxx]] [Dxx]\n",argv[0]);
printf(" where C = A|a write vv to ARxx\n");
printf(" = C|c write vv to CRxx\n");
printf(" = F|f write vv to FRxx (6555x only)\n");
printf(" = G|g write vv to GRxx\n");
printf(" = M|m write vv to MRxx (6555x only)\n");
printf(" = S|s write vv to SRxx\n");
printf(" = X|x write vv to XRxx\n");
printf(" where D = Y|y write xx to FCR\n");
printf(" = Z|z write vv to MSR\n");
printf(" xx is in hexadecimal\n");
printf(" vv is in hexadecimal or '?' for query\n");
}
SET_IOPL();
for(i = 1; i < argc; i++){
value = 0;
str = argv[i];
c = *str++;
switch (c) {
case 'f':
case 'F':
cport = 'F';
port = 0x3D0;
break;
case 'c':
case 'C':
cport = 'C';
port = 0x3D4;
break;
case 'x':
case 'X':
cport = 'X';
port = 0x3D6;
break;
case 'g':
case 'G':
cport = 'G';
port = 0x3CE;
break;
case 'a':
case 'A':
cport = 'A';
port = 0x3C0;
break;
case 's':
case 'S':
cport = 'S';
port = 0x3C4;
break;
case 'm':
case 'M':
cport = 'M';
port = 0x3D2;
break;
case 'y':
case 'Y':
cport = 'Y';
port = 0x3DA;
port1 = 0x3CA;
break;
case 'z':
case 'Z':
cport = 'Z';
port = 0x3C2;
port1 = 0x3CC;
break;
default:
continue;
break;
}
if ((cport != 'Z') && (cport != 'Y')) index = inb(port);
while ((c = *str++)) {
if (c == '?') {
query = 1;
}
if(c >= '0' && c <= '9')
value = (value << 4) | (c - '0'); /*ASCII assumed*/
else if(c >= 'A' && c < 'G')
value = (value << 4) | (c - 'A'+10); /*ASCII assumed*/
else if(c >= 'a' && c < 'g')
value = (value << 4) | (c - 'a'+10); /*ASCII assumed*/
}
if ((cport != 'Z') && (cport != 'Y')) outb(port,value&0xFF);
if (query) {
if ((cport != 'Z') && (cport != 'Y'))
printf("%cR%X: 0x%X\n", cport, value & 0xFF,
inb(port+1)&0xFF);
else
if (cport == 'Z')
printf("MSR: 0x%X\n", inb(port1)&0xFF);
else
printf("FCR: 0x%X\n", inb(port1)&0xFF);
} else {
if ((cport != 'Z') && (cport != 'Y')) {
printf("%cR%X: 0x%X -> 0x%X\n", cport, value & 0xFF,
inb(port+1)&0xFF, (value&0xFF00)>>8);
outw(port, value);
outb(port, index &0xFF);
} else {
if (cport == 'Z')
printf("MSR: 0x%X -> 0x%X\n", inb(port1)&0xFF, value&0xFF);
else
printf("FCR: 0x%X -> 0x%X\n", inb(port1)&0xFF, value&0xFF);
outb(port, value & 0xFF);
}
}
}
RESET_IOPL();
return 0;
}

356
hw/xfree86/drivers/video/chips/util/modClock.c Normal file
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#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <fnmatch.h>
#include "iopl.h"
#define tolerance 0.01 /* +/- 1% */
#define CT65520 0x1
#define CT65525 0x2
#define CT65530 0x3
#define CT64200 0x4
#define CT65535 0x11
#define CT65540 0x12
#define CT65545 0x13
#define CT65546 0x14
#define CT65548 0x15
#define CT64300 0x16
#define CT65550 0x31
#define CT65554 0x32
#define CT65555 0x33
#define CT68554 0x34
#define CT69000 0x35
#define CT69030 0x36
#define IS_Programmable(X) X&0x10
#define IS_HiQV(X) X&0x20
#define DotClk 0
#define MemClk 1
#define IS_MemClk(X) X&0x1
static int compute_clock (
unsigned int ChipType,
double target,
double Fref,
unsigned int ClkMaxN,
unsigned int ClkMaxM,
unsigned int *bestM,
unsigned int *bestN,
unsigned int *bestP,
unsigned int *bestPSN) {
unsigned int M, N, P, PSN, PSNx;
double bestError = 0, abest = 42, bestFout = 0;
double Fvco, Fout;
double error, aerror;
unsigned int M_min = 3;
unsigned int M_max = ClkMaxM;
if (target < 1e6){
fprintf (stderr, "MHz assumed, changed to %g MHz\n", target);
target *= 1e6;
}
if (target > 220.0e6) {
fprintf (stderr, "too large\n");
return 1;
}
/* Other parameters available on the 65548 but not the 65545, and
not documented in the Clock Synthesizer doc in rev 1.0 of the
65548 datasheet:
+ XR30[4] = 0, VCO divider loop uses divide by 4 (same as 65545)
1, VCO divider loop uses divide by 16
+ XR30[5] = 1, reference clock is divided by 5
I haven't put in any support for those here. For simplicity,
they should be set to 0 on the 65548, and left untouched on
earlier chips. */
for (PSNx = ((ChipType == CT69000) || (ChipType == CT69030)) ? 1 : 0;
PSNx <= 1; PSNx++) {
unsigned int low_N, high_N;
double Fref4PSN;
PSN = PSNx ? 1 : 4;
low_N = 3;
high_N = ClkMaxN;
while (Fref / (PSN * low_N) > (((ChipType == CT69000) ||
(ChipType == CT69030)) ? 5.0e6 : 2.0e6))
low_N++;
while (Fref / (PSN * high_N) < 150.0e3)
high_N--;
Fref4PSN = Fref * 4 / PSN;
for (N = low_N; N <= high_N; N++) {
double tmp = Fref4PSN / N;
for (P = (IS_HiQV(ChipType) && (ChipType != CT69000) &&
(ChipType != CT69030)) ? 1 : 0; P <= 5; P++) {
double Fvco_desired = target * (1 << P);
double M_desired = Fvco_desired / tmp;
/* Which way will M_desired be rounded? Do all three just to
be safe. */
unsigned int M_low = M_desired - 1;
unsigned int M_hi = M_desired + 1;
if (M_hi < M_min || M_low > M_max)
continue;
if (M_low < M_min)
M_low = M_min;
if (M_hi > M_max)
M_hi = M_max;
for (M = M_low; M <= M_hi; M++) {
Fvco = tmp * M;
if (Fvco <= ((ChipType == CT69000) || (ChipType == CT69030) ?
100e6 : 48.0e6))
continue;
if (Fvco > 220.0e6)
break;
Fout = Fvco / (1 << P);
error = (target - Fout) / target;
aerror = (error < 0) ? -error : error;
if (aerror < abest) {
abest = aerror;
bestError = error;
*bestM = M;
*bestN = N;
*bestP = P;
*bestPSN = PSN;
bestFout = Fout;
}
}
}
}
}
if (abest < tolerance) {
printf ("best: M=%d N=%d P=%d PSN=%d\n", *bestM, *bestN, *bestP, *bestPSN);
if (bestFout > 1.0e6)
printf ("Fout = %g MHz", bestFout / 1.0e6);
else if (bestFout > 1.0e3)
printf ("Fout = %g kHz", bestFout / 1.0e3);
else
printf ("Fout = %g Hz", bestFout);
printf (", error = %g\n", bestError);
return 0;
}
printf ("can't do it with less than %g error\n", bestError);
return 1;
}
static int set_clock(
unsigned int ChipType,
unsigned int ClockType,
unsigned int ProgClock,
unsigned int M,
unsigned int N,
unsigned int P,
unsigned int PSN) {
unsigned int tmp, idx;
SET_IOPL();
idx = inb(0x3D6);
if (IS_HiQV(ChipType)) {
if (IS_MemClk(ClockType)) {
printf ("XRCC = 0x%02X\n", M - 2);
printf ("XRCD = 0x%02X\n", N - 2);
printf ("XRCE = 0x%02X\n", (0x80 | (P * 16 + (PSN == 1))));
outb(0x3D6, 0xCE); /* Select Fix MClk before */
tmp = inb(0x3D7);
outb(0x3D7, tmp & 0x7F);
outb(0x3D6, 0xCC);
outb(0x3D7, (M - 2));
outb(0x3D6, 0xCD);
outb(0x3D7, (N - 2));
outb(0x3D6, 0xCE);
outb(0x3D7, (0x80 | (P * 16 + (PSN == 1))));
} else {
printf ("XR%X = 0x%02X\n", 0xC0 + 4 * ProgClock, M - 2);
printf ("XR%X = 0x%02X\n", 0xC1 + 4 * ProgClock, N - 2);
printf ("XR%X = 0x%02X\n", 0xC2 + 4 * ProgClock, 0);
printf ("XR%X = 0x%02X\n", 0xC3 + 4 * ProgClock, P * 16 + (PSN == 1));
outb(0x3D6, 0xC0 + 4 * ProgClock);
outb(0x3D7, (M - 2));
outb(0x3D6, 0xC1 + 4 * ProgClock);
outb(0x3D7, (N - 2));
outb(0x3D6, 0xC2 + 4 * ProgClock);
outb(0x3D7, 0x0);
outb(0x3D6, 0xC3 + 4 * ProgClock);
outb(0x3D7, (P * 16 + (PSN == 1)));
}
} else {
printf ("XR30 = 0x%02X\n", P * 2 + (PSN == 1));
printf ("XR31 = 0x%02X\n", M - 2);
printf ("XR32 = 0x%02X\n", N - 2);
outb(0x3D6, 0x33);
tmp = inb(0x3D7);
if (IS_MemClk(ClockType)) {
outb(0x3D7, tmp | 0x20);
} else {
outb(0x3D7, tmp & ~0x20);
}
outb(0x3D6, 0x30);
outb(0x3D7, (P * 2 + (PSN == 1)));
outb(0x3D6, 0x31);
outb(0x3D7, (M - 2));
outb(0x3D6, 0x32);
outb(0x3D7, (N - 2));
outb(0x3D6, 0x33);
outb(0x3D7, tmp);
}
outb(0x3D6, idx);
RESET_IOPL();
return 0;
}
static unsigned int probe_chip(void) {
unsigned int ChipType, temp;
SET_IOPL();
outb(0x3D6, 0x00);
temp = inb(0x3D7);
ChipType = 0;
if (temp != 0xA5) {
if ((temp & 0xF0) == 0x70) {
ChipType = CT65520;
}
if ((temp & 0xF0) == 0x80) { /* could also be a 65525 */
ChipType = CT65530;
}
if ((temp & 0xF0) == 0xA0) {
ChipType = CT64200;
}
if ((temp & 0xF0) == 0xB0) {
ChipType = CT64300;
}
if ((temp & 0xF0) == 0xC0) {
ChipType = CT65535;
}
if ((temp & 0xF8) == 0xD0) {
ChipType = CT65540;
}
if ((temp & 0xF8) == 0xD8) {
switch (temp & 0x07) {
case 3:
ChipType = CT65546;
break;
case 4:
ChipType = CT65548;
break;
default:
ChipType = CT65545;
}
}
}
/* At this point the chip could still be a HiQV, so check for
* that. This test needs some looking at */
if ((temp != 0) && (ChipType == 0)) {
outb(0x3D6, 0x02);
temp = inb(0x03D7);
if (temp == 0xE0) {
ChipType = CT65550;
}
if (temp == 0xE4) {
ChipType = CT65554;
}
if (temp == 0xE5) {
ChipType = CT65555;
}
if (temp == 0xF4) {
ChipType = CT68554;
}
if (temp == 0xC0) {
ChipType = CT69000;
}
if (temp == 0x30) {
outb(0x3D6, 0x03);
temp = inb(0x03D7);
if (temp == 0x0C) ChipType = CT69030;
}
}
RESET_IOPL();
if (ChipType == 0) { /* failure */
fprintf(stderr, "Not a Chips and Technologies Chipset\n");
}
return ChipType;
}
int main (int argc, char *argv[]) {
double target;
double Fref = 14318180;
unsigned int M, N, P, PSN, ChipType, ClockType, progclock;
switch (argc) {
case 2:
progclock = 2;
target = atof (argv[1]);
break;
case 3:
progclock = abs(atof (argv[1]));
target = atof (argv[2]);
break;
default:
fprintf (stderr, "usage: %s [-0|-1|-2] freq\n", argv[0]);
return 1;
}
ClockType = DotClk;
if (! fnmatch("*memClock",argv[0],FNM_PATHNAME)) {
ClockType = MemClk;
}
ChipType = probe_chip();
if (!ChipType) {
return 1;
}
if (!(IS_Programmable(ChipType))) {
fprintf(stderr, "No programmable Clock!\n");
return 1;
}
if (IS_HiQV(ChipType)) {
if (! compute_clock(ChipType, target, Fref, 63, 127, &M, &N, &P, &PSN)) {
return set_clock(ChipType, ClockType, progclock, M, N, P, PSN);
} else {
return 1;
}
} else {
if (! compute_clock(ChipType, target, Fref, 127, 127, &M, &N, &P, &PSN)) {
return set_clock(ChipType, ClockType, progclock, M, N, P, PSN);
} else {
return 1;
}
}
}