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Eric Anholt
200
src/nvreg.h
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200
src/nvreg.h
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/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */
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/*
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* Copyright 1996-1997 David J. McKay
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h,v 1.6 2002/01/25 21:56:06 tsi Exp $ */
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#ifndef __NVREG_H_
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#define __NVREG_H_
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/* Little macro to construct bitmask for contiguous ranges of bits */
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#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
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#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
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/* Macro to set specific bitfields (mask has to be a macro x:y) ! */
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#define SetBF(mask,value) ((value) << (0?mask))
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#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
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#define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \
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| SetBF(mask,value)))
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#define DEVICE_BASE(device) (0?NV##_##device)
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#define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1)
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/* This is where we will have to have conditional compilation */
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#define DEVICE_ACCESS(device,reg) \
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nv##device##Port[((NV_##device##_##reg)-DEVICE_BASE(device))/4]
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#define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value)
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#define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg)
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#define DEVICE_PRINT(device,reg) \
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ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
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#define DEVICE_DEF(device,mask,value) \
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SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
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#define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value)
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#define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask)
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#define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value)
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#define PDAC_Read(reg) DEVICE_READ(PDAC,reg)
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#define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg)
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#define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value)
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#define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value)
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#define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask)
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#define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value)
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#define PFB_Read(reg) DEVICE_READ(PFB,reg)
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#define PFB_Print(reg) DEVICE_PRINT(PFB,reg)
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#define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value)
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#define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value)
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#define PFB_Mask(mask) DEVICE_MASK(PFB,mask)
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#define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value)
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#define PRM_Read(reg) DEVICE_READ(PRM,reg)
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#define PRM_Print(reg) DEVICE_PRINT(PRM,reg)
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#define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value)
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#define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value)
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#define PRM_Mask(mask) DEVICE_MASK(PRM,mask)
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#define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value)
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#define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg)
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#define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg)
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#define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value)
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#define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value)
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#define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask)
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#define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value)
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#define PDMA_Read(reg) DEVICE_READ(PDMA,reg)
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#define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg)
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#define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value)
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#define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value)
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#define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask)
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#define PTIMER_Write(reg,value) DEVICE_WRITE(PTIMER,reg,value)
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#define PTIMER_Read(reg) DEVICE_READ(PTIMER,reg)
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#define PTIMER_Print(reg) DEVICE_PRINT(PTIMER,reg)
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#define PTIMER_Def(mask,value) DEVICE_DEF(PTIMER,mask,value)
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#define PTIMER_Val(mask,value) DEVICE_VALUE(PTIEMR,mask,value)
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#define PTIMER_Mask(mask) DEVICE_MASK(PTIMER,mask)
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#define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value)
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#define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg)
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#define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg)
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#define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value)
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#define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value)
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#define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask)
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#define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value)
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#define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg)
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#define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg)
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#define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value)
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#define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value)
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#define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask)
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#define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value)
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#define PRAM_Read(reg) DEVICE_READ(PRAM,reg)
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#define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg)
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#define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value)
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#define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value)
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#define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask)
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#define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value)
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#define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg)
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#define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg)
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#define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value)
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#define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value)
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#define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask)
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#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
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#define PMC_Read(reg) DEVICE_READ(PMC,reg)
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#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
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#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
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#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
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#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
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#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
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#define PMC_Read(reg) DEVICE_READ(PMC,reg)
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#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
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#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
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#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
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#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
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#define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value)
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#define PBUS_Read(reg) DEVICE_READ(PBUS,reg)
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#define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg)
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#define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value)
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#define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value)
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#define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask)
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#define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value)
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#define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg)
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#define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg)
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#define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value)
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#define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value)
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#define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask)
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#define PDAC_ReadExt(reg) \
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((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
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(PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
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(PDAC_Read(INDEX_DATA)))
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#define PDAC_WriteExt(reg,value)\
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((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
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(PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
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(PDAC_Write(INDEX_DATA,(value))))
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#define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value)
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#define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value)
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#define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask)
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/* These are the variables which actually point at the register blocks */
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extern volatile unsigned *nvPDACPort; /* Points to the DAC */
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extern volatile unsigned *nvPFBPort; /* Points to the Frame buffer */
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extern volatile unsigned *nvPRMPort; /* Points to real mode stuff */
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extern volatile unsigned *nvPGRAPHPort; /* Graphics unit */
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extern volatile unsigned *nvPDMAPort; /* DMA engine */
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extern volatile unsigned *nvPFIFOPort; /* FIFO registers */
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extern volatile unsigned *nvPTIMERPort; /* TIMER registers */
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extern volatile unsigned *nvPEXTDEVPort; /* EXTDEV registers */
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extern volatile unsigned *nvPRAMPort; /* Priviliged RAM registers */
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extern volatile unsigned *nvPRAMFCPort; /* Priviliged RAM (Fifo) */
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extern volatile unsigned *nvPRAMHTPort; /* Priviliged RAM (hash) */
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extern volatile unsigned *nvPMCPort; /* Priviliged RAM (hash) */
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extern volatile unsigned *nvCHAN0Port; /* User channel 0 */
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extern volatile unsigned *nvPRAMDACPort; /* Points to the RAMDAC */
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extern volatile unsigned *nvPRAMINPort; /* Privileges instance memory */
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extern volatile unsigned *nvPBUSPort; /* Priviled Bus */
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extern volatile unsigned *nvPNVMPort; /* Priviled Bus */
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extern volatile unsigned *dumb; /* FrameBuffer - hack!!!! */
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typedef enum {NV1,NV3,NV4,NV10,NumNVChips} NVChipType;
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NVChipType GetChipType(void);
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#endif
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82
src/nvvga.h
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82
src/nvvga.h
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@@ -0,0 +1,82 @@
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/*
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* Copyright 1996-1997 David J. McKay
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nvvga.h,v 1.2 2001/11/19 15:33:41 tsi Exp $ */
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#ifndef __NVVGA_H__
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#define __NVVGA_H__
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#include "riva_hw.h"
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#define PALETTE_SIZE 256
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#define NV_PDAC_CURSOR_SIZE 32
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#define NV_PDAC_CURSOR_PLANE_SIZE (NV_PDAC_CURSOR_SIZE*4)
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/* This is the structure for the NV1. It is not a VGA based core */
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typedef struct {
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unsigned char Nparam, Mparam, Oparam, Pparam;
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unsigned char NparamMPLL, MparamMPLL, OparamMPLL, PparamMPLL;
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unsigned char dacConfReg0;
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unsigned char dacConfReg1;
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unsigned char dacRgbPalCtrl;
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unsigned long confReg0;
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unsigned long green0; /* DPMS and sync polarity control */
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unsigned long memoryTrace;
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unsigned long startAddr; /* Where to start reading out from the buffer */
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/* All the following registers control the display */
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unsigned long prmConfig0; /* Controls if text mode on or off */
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unsigned long horFrontPorch; /* Front porch in pixels */
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unsigned long horSyncWidth; /* Sync Width in pixels */
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unsigned long horBackPorch; /* horizontal back porch in in pixels */
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unsigned long horDispWidth; /* Horizontal display width in pixels */
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unsigned long verFrontPorch; /* Vertical front porch in lines */
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unsigned long verSyncWidth; /* Vertical sync width in lines */
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unsigned long verBackPorch; /* Vertical back porch in lines */
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unsigned long verDispWidth; /* Vertical display width in lines */
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/* Hardware cursor registers */
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unsigned char cursorCtrl;
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unsigned char xHi,xLo,yHi,yLo;
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unsigned char colour1[3]; /* RGB values for cursor planes */
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unsigned char colour2[3];
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unsigned char colour3[3];
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unsigned char plane0[NV_PDAC_CURSOR_PLANE_SIZE];
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unsigned char plane1[NV_PDAC_CURSOR_PLANE_SIZE];
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unsigned char palette[PALETTE_SIZE][3];
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}NV1Registers;
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/*
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* Driver data structures.
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*/
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typedef struct {
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/* vgaHWRec std; good old IBM VGA */
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int vgaValid; /* is the above state valid?? */
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NVChipType type; /* What the union holds */
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union {
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NV1Registers nv1;
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RIVA_HW_STATE RivaState;
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}regs;
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} vgaNVRec, *vgaNVPtr;
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#endif
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