The automatic panel scaling appears to choose bad sampling on some GM965
hardware for 1:1 mapping modes, and there's no real sense in having it on
if we just want 1:1.
Make sure there is some border area to use by changing how the pipe is
configured, then pick a scanline in the middle of the border for load
detection. This lets the load detect code use an active pipe instead of
requiring an idle one.
Just as with i9xx LVDS, the i855 LVDS can operate in dual-channel mode with
a modified P2 divisor value (7 instead of 14). Just using the existing 9xx
code for 855 appears to work fine.
LVDS mode changes how the PLL works in fairly dramatic ways; the debug code
wasn't properly accounting for those differences resulting in fairly bogus
debug output.
The x40 LVDS mode has a 49.6Hz vertical refresh. Waiting for only 20ms can
sometimes cause the driver to start programming the hardware before the
vblank has occurred, which will lock up the i855 chipset. Extend this to
30ms (the maximum timeout used by the BIOS) to ensure this doesn't happen.
Detecting actual vblank occurance using the various status registers should
also be possible but isn't yet working.
The backlight control in the LVDS controller can either operate in 'normal'
mode or 'legacy' mode. In legacy mode, it uses the PCI config space register
0xf4 which can range from 0 to 0xff. In normal mode, it reads the range and
current value from the BLC_PWM_CTL register.
Be sure to check G33 chip type in:
- sdvo output
- Y-major tile
- crt detect
- and xaa composite
Sorry for that I should have fixed them very earlier...
On 855, letting crtc_mode_set enable the plane and pipe will occasionally
hang the chip. Instead, wait for crtc_enable to light things up. For 9xx,
leave things alone.
Now, all 3D pipeline consumers in the driver just call
IntelEmitInvariantState(), which handles basic state setup, the caching of that
state setup, and notifying DRI clients. This also removes a mistaken idle
wait in the Render code which was papering over the brokenness in the context
switching.
- The screen dimensions were used for the clipping despite drawing being done
to any pixmap, not necessarily the screen.
- One piece of state setup was not documented anywhere, and isn't used in other
3d hardware paths that also work.
- A 3DSTATE_MODES_1 command (830-class only) was issued even though it no
longer exists.
These chipsets require that the hardware status page be referenced by an offset
in the GTT rather than a physical memory address, so the X Server allocates it
rather than the DRM.
Ok, so moving video from pipe A to pipe B still requires that pipe A be
active during the transition. Instead of trying to be fancy, just ensure
that pipe A is running on each transition to pipe B.
