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Initial SI support.

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Defaults to shadowfb. 3D acceleration is available with glamor. 2D
acceleration is disabled until the radeonsi driver can handle glamor's
shaders.

v2: add chip flags (Alex Deucher)

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Michel Dänzer
2012-07-05 20:14:48 +02:00
committed by Michel Dänzer
parent e9edd2f500
commit ef8a404391
16 changed files with 2390 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
man/radeon.man
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@@ -180,6 +180,12 @@ Radeon HD 6430/6450/6470/6490
Radeon HD 6950/6970/6990
.TP 12
.B ARUBA
.TP 12
.B TAHITI
.TP 12
.B PITCAIRN
.TP 12
.B VERDE
.PD
.SH CONFIGURATION DETAILS
Please refer to __xconfigfile__(__filemansuffix__) for general configuration

2
src/Makefile.am
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@@ -68,6 +68,7 @@ if GLAMOR
AM_CFLAGS += @LIBGLAMOR_CFLAGS@
radeon_drv_la_LIBADD += @LIBGLAMOR_LIBS@
radeon_drv_la_SOURCES += \
radeon_glamor_wrappers.c \
radeon_glamor.c
endif
@@ -96,6 +97,7 @@ EXTRA_DIST = \
radeon_exa_funcs.c \
radeon_exa_shared.h \
radeon_glamor.h \
radeon_glamor_wrappers.h \
radeon.h \
radeon_probe.h \
radeon_reg.h \

39
src/ati_pciids_gen.h
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@@ -617,3 +617,42 @@
#define PCI_CHIP_ARUBA_99A0 0x99A0
#define PCI_CHIP_ARUBA_99A2 0x99A2
#define PCI_CHIP_ARUBA_99A4 0x99A4
#define PCI_CHIP_TAHITI_6780 0x6780
#define PCI_CHIP_TAHITI_6784 0x6784
#define PCI_CHIP_TAHITI_6788 0x6788
#define PCI_CHIP_TAHITI_678A 0x678A
#define PCI_CHIP_TAHITI_6790 0x6790
#define PCI_CHIP_TAHITI_6798 0x6798
#define PCI_CHIP_TAHITI_6799 0x6799
#define PCI_CHIP_TAHITI_679A 0x679A
#define PCI_CHIP_TAHITI_679E 0x679E
#define PCI_CHIP_TAHITI_679F 0x679F
#define PCI_CHIP_PITCAIRN_6800 0x6800
#define PCI_CHIP_PITCAIRN_6801 0x6801
#define PCI_CHIP_PITCAIRN_6802 0x6802
#define PCI_CHIP_PITCAIRN_6808 0x6808
#define PCI_CHIP_PITCAIRN_6809 0x6809
#define PCI_CHIP_PITCAIRN_6810 0x6810
#define PCI_CHIP_PITCAIRN_6818 0x6818
#define PCI_CHIP_PITCAIRN_6819 0x6819
#define PCI_CHIP_PITCAIRN_684C 0x684C
#define PCI_CHIP_VERDE_6820 0x6820
#define PCI_CHIP_VERDE_6821 0x6821
#define PCI_CHIP_VERDE_6823 0x6823
#define PCI_CHIP_VERDE_6824 0x6824
#define PCI_CHIP_VERDE_6825 0x6825
#define PCI_CHIP_VERDE_6826 0x6826
#define PCI_CHIP_VERDE_6827 0x6827
#define PCI_CHIP_VERDE_6828 0x6828
#define PCI_CHIP_VERDE_6829 0x6829
#define PCI_CHIP_VERDE_682B 0x682B
#define PCI_CHIP_VERDE_682D 0x682D
#define PCI_CHIP_VERDE_682F 0x682F
#define PCI_CHIP_VERDE_6830 0x6830
#define PCI_CHIP_VERDE_6831 0x6831
#define PCI_CHIP_VERDE_6837 0x6837
#define PCI_CHIP_VERDE_6838 0x6838
#define PCI_CHIP_VERDE_6839 0x6839
#define PCI_CHIP_VERDE_683B 0x683B
#define PCI_CHIP_VERDE_683D 0x683D
#define PCI_CHIP_VERDE_683F 0x683F

39
src/pcidb/ati_pciids.csv
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@@ -618,3 +618,42 @@
"0x99A0","ARUBA_99A0","ARUBA",1,,,,,"ARUBA"
"0x99A2","ARUBA_99A2","ARUBA",1,,,,,"ARUBA"
"0x99A4","ARUBA_99A4","ARUBA",,,,,,"ARUBA"
"0x6780","TAHITI_6780","TAHITI",,,,,,"TAHITI"
"0x6784","TAHITI_6784","TAHITI",,,,,,"TAHITI"
"0x6788","TAHITI_6788","TAHITI",,,,,,"TAHITI"
"0x678A","TAHITI_678A","TAHITI",,,,,,"TAHITI"
"0x6790","TAHITI_6790","TAHITI",,,,,,"TAHITI"
"0x6798","TAHITI_6798","TAHITI",,,,,,"TAHITI"
"0x6799","TAHITI_6799","TAHITI",,,,,,"TAHITI"
"0x679A","TAHITI_679A","TAHITI",,,,,,"TAHITI"
"0x679E","TAHITI_679E","TAHITI",,,,,,"TAHITI"
"0x679F","TAHITI_679F","TAHITI",,,,,,"TAHITI"
"0x6800","PITCAIRN_6800","PITCAIRN",1,,,,,"PITCAIRN"
"0x6801","PITCAIRN_6801","PITCAIRN",1,,,,,"PITCAIRN"
"0x6802","PITCAIRN_6802","PITCAIRN",1,,,,,"PITCAIRN"
"0x6808","PITCAIRN_6808","PITCAIRN",,,,,,"PITCAIRN"
"0x6809","PITCAIRN_6809","PITCAIRN",,,,,,"PITCAIRN"
"0x6810","PITCAIRN_6810","PITCAIRN",,,,,,"PITCAIRN"
"0x6818","PITCAIRN_6818","PITCAIRN",,,,,,"PITCAIRN"
"0x6819","PITCAIRN_6819","PITCAIRN",,,,,,"PITCAIRN"
"0x684C","PITCAIRN_684C","PITCAIRN",,,,,,"PITCAIRN"
"0x6820","VERDE_6820","VERDE",1,,,,,"VERDE"
"0x6821","VERDE_6821","VERDE",1,,,,,"VERDE"
"0x6823","VERDE_6823","VERDE",1,,,,,"VERDE"
"0x6824","VERDE_6824","VERDE",1,,,,,"VERDE"
"0x6825","VERDE_6825","VERDE",1,,,,,"VERDE"
"0x6826","VERDE_6826","VERDE",1,,,,,"VERDE"
"0x6827","VERDE_6827","VERDE",1,,,,,"VERDE"
"0x6828","VERDE_6828","VERDE",,,,,,"VERDE"
"0x6829","VERDE_6829","VERDE",,,,,,"VERDE"
"0x682B","VERDE_682B","VERDE",1,,,,,"VERDE"
"0x682D","VERDE_682D","VERDE",1,,,,,"VERDE"
"0x682F","VERDE_682F","VERDE",1,,,,,"VERDE"
"0x6830","VERDE_6830","VERDE",1,,,,,"VERDE"
"0x6831","VERDE_6831","VERDE",1,,,,,"VERDE"
"0x6837","VERDE_6837","VERDE",,,,,,"VERDE"
"0x6838","VERDE_6838","VERDE",,,,,,"VERDE"
"0x6839","VERDE_6839","VERDE",,,,,,"VERDE"
"0x683B","VERDE_683B","VERDE",,,,,,"VERDE"
"0x683D","VERDE_683D","VERDE",,,,,,"VERDE"
"0x683F","VERDE_683F","VERDE",,,,,,"VERDE"
1 #pciid define family mobility igp nocrtc2 Nointtvout singledac name
618 0x99A0 ARUBA_99A0 ARUBA 1 ARUBA
619 0x99A2 ARUBA_99A2 ARUBA 1 ARUBA
620 0x99A4 ARUBA_99A4 ARUBA ARUBA
621 0x6780 TAHITI_6780 TAHITI TAHITI
622 0x6784 TAHITI_6784 TAHITI TAHITI
623 0x6788 TAHITI_6788 TAHITI TAHITI
624 0x678A TAHITI_678A TAHITI TAHITI
625 0x6790 TAHITI_6790 TAHITI TAHITI
626 0x6798 TAHITI_6798 TAHITI TAHITI
627 0x6799 TAHITI_6799 TAHITI TAHITI
628 0x679A TAHITI_679A TAHITI TAHITI
629 0x679E TAHITI_679E TAHITI TAHITI
630 0x679F TAHITI_679F TAHITI TAHITI
631 0x6800 PITCAIRN_6800 PITCAIRN 1 PITCAIRN
632 0x6801 PITCAIRN_6801 PITCAIRN 1 PITCAIRN
633 0x6802 PITCAIRN_6802 PITCAIRN 1 PITCAIRN
634 0x6808 PITCAIRN_6808 PITCAIRN PITCAIRN
635 0x6809 PITCAIRN_6809 PITCAIRN PITCAIRN
636 0x6810 PITCAIRN_6810 PITCAIRN PITCAIRN
637 0x6818 PITCAIRN_6818 PITCAIRN PITCAIRN
638 0x6819 PITCAIRN_6819 PITCAIRN PITCAIRN
639 0x684C PITCAIRN_684C PITCAIRN PITCAIRN
640 0x6820 VERDE_6820 VERDE 1 VERDE
641 0x6821 VERDE_6821 VERDE 1 VERDE
642 0x6823 VERDE_6823 VERDE 1 VERDE
643 0x6824 VERDE_6824 VERDE 1 VERDE
644 0x6825 VERDE_6825 VERDE 1 VERDE
645 0x6826 VERDE_6826 VERDE 1 VERDE
646 0x6827 VERDE_6827 VERDE 1 VERDE
647 0x6828 VERDE_6828 VERDE VERDE
648 0x6829 VERDE_6829 VERDE VERDE
649 0x682B VERDE_682B VERDE 1 VERDE
650 0x682D VERDE_682D VERDE 1 VERDE
651 0x682F VERDE_682F VERDE 1 VERDE
652 0x6830 VERDE_6830 VERDE 1 VERDE
653 0x6831 VERDE_6831 VERDE 1 VERDE
654 0x6837 VERDE_6837 VERDE VERDE
655 0x6838 VERDE_6838 VERDE VERDE
656 0x6839 VERDE_6839 VERDE VERDE
657 0x683B VERDE_683B VERDE VERDE
658 0x683D VERDE_683D VERDE VERDE
659 0x683F VERDE_683F VERDE VERDE

39
src/radeon_chipinfo_gen.h
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@@ -537,4 +537,43 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x99A0, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
{ 0x99A2, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
{ 0x99A4, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
{ 0x6780, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
{ 0x6784, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
{ 0x6788, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
{ 0x678A, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
{ 0x6790, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
{ 0x6798, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
{ 0x6799, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
{ 0x679A, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
{ 0x679E, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
{ 0x679F, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
{ 0x6800, CHIP_FAMILY_PITCAIRN, 1, 0, 0, 0, 0 },
{ 0x6801, CHIP_FAMILY_PITCAIRN, 1, 0, 0, 0, 0 },
{ 0x6802, CHIP_FAMILY_PITCAIRN, 1, 0, 0, 0, 0 },
{ 0x6808, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
{ 0x6809, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
{ 0x6810, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
{ 0x6818, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
{ 0x6819, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
{ 0x684C, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
{ 0x6820, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
{ 0x6821, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
{ 0x6823, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
{ 0x6824, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
{ 0x6825, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
{ 0x6826, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
{ 0x6827, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
{ 0x6828, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
{ 0x6829, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
{ 0x682B, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
{ 0x682D, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
{ 0x682F, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
{ 0x6830, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
{ 0x6831, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
{ 0x6837, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
{ 0x6838, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
{ 0x6839, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
{ 0x683B, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
{ 0x683D, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
{ 0x683F, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
};

39
src/radeon_chipset_gen.h
View File

@@ -537,5 +537,44 @@ SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_ARUBA_99A0, "ARUBA" },
{ PCI_CHIP_ARUBA_99A2, "ARUBA" },
{ PCI_CHIP_ARUBA_99A4, "ARUBA" },
{ PCI_CHIP_TAHITI_6780, "TAHITI" },
{ PCI_CHIP_TAHITI_6784, "TAHITI" },
{ PCI_CHIP_TAHITI_6788, "TAHITI" },
{ PCI_CHIP_TAHITI_678A, "TAHITI" },
{ PCI_CHIP_TAHITI_6790, "TAHITI" },
{ PCI_CHIP_TAHITI_6798, "TAHITI" },
{ PCI_CHIP_TAHITI_6799, "TAHITI" },
{ PCI_CHIP_TAHITI_679A, "TAHITI" },
{ PCI_CHIP_TAHITI_679E, "TAHITI" },
{ PCI_CHIP_TAHITI_679F, "TAHITI" },
{ PCI_CHIP_PITCAIRN_6800, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6801, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6802, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6808, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6809, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6810, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6818, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_6819, "PITCAIRN" },
{ PCI_CHIP_PITCAIRN_684C, "PITCAIRN" },
{ PCI_CHIP_VERDE_6820, "VERDE" },
{ PCI_CHIP_VERDE_6821, "VERDE" },
{ PCI_CHIP_VERDE_6823, "VERDE" },
{ PCI_CHIP_VERDE_6824, "VERDE" },
{ PCI_CHIP_VERDE_6825, "VERDE" },
{ PCI_CHIP_VERDE_6826, "VERDE" },
{ PCI_CHIP_VERDE_6827, "VERDE" },
{ PCI_CHIP_VERDE_6828, "VERDE" },
{ PCI_CHIP_VERDE_6829, "VERDE" },
{ PCI_CHIP_VERDE_682B, "VERDE" },
{ PCI_CHIP_VERDE_682D, "VERDE" },
{ PCI_CHIP_VERDE_682F, "VERDE" },
{ PCI_CHIP_VERDE_6830, "VERDE" },
{ PCI_CHIP_VERDE_6831, "VERDE" },
{ PCI_CHIP_VERDE_6837, "VERDE" },
{ PCI_CHIP_VERDE_6838, "VERDE" },
{ PCI_CHIP_VERDE_6839, "VERDE" },
{ PCI_CHIP_VERDE_683B, "VERDE" },
{ PCI_CHIP_VERDE_683D, "VERDE" },
{ PCI_CHIP_VERDE_683F, "VERDE" },
{ -1, NULL }
};

4
src/radeon_dri2.c
View File

@@ -1400,7 +1400,9 @@ radeon_dri2_screen_init(ScreenPtr pScreen)
info->dri2.device_name = drmGetDeviceNameFromFd(info->dri2.drm_fd);
if ( (info->ChipFamily >= CHIP_FAMILY_R600) ) {
if ( (info->ChipFamily >= CHIP_FAMILY_TAHITI) ) {
dri2_info.driverName = SI_DRIVER_NAME;
} else if ( (info->ChipFamily >= CHIP_FAMILY_R600) ) {
dri2_info.driverName = R600_DRIVER_NAME;
} else if ( (info->ChipFamily >= CHIP_FAMILY_R300) ) {
dri2_info.driverName = R300_DRIVER_NAME;

88
src/radeon_glamor.c
View File

@@ -135,18 +135,85 @@ radeon_glamor_create_textured_pixmap(PixmapPtr pixmap)
return FALSE;
}
Bool radeon_glamor_pixmap_is_offscreen(PixmapPtr pixmap)
{
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
return priv && priv->bo;
}
Bool radeon_glamor_prepare_access(PixmapPtr pixmap, glamor_access_t access)
{
ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen);
RADEONInfoPtr info = RADEONPTR(scrn);
struct radeon_bo *bo;
int ret;
if (access == GLAMOR_GPU_ACCESS_RW || access == GLAMOR_GPU_ACCESS_RO)
return info->ChipFamily < CHIP_FAMILY_TAHITI;
bo = radeon_get_pixmap_bo(pixmap);
if (bo) {
/* When falling back to swrast, flush all pending operations */
if (info->ChipFamily < CHIP_FAMILY_TAHITI)
radeon_glamor_flush(scrn);
ret = radeon_bo_map(bo, 1);
if (ret) {
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
"%s: bo map (tiling_flags %d, access %d) failed: %s\n",
__FUNCTION__,
radeon_get_pixmap_private(pixmap)->tiling_flags,
access,
strerror(-ret));
return FALSE;
}
pixmap->devPrivate.ptr = bo->ptr;
}
return TRUE;
}
void
radeon_glamor_finish_access(PixmapPtr pixmap, glamor_access_t access)
{
struct radeon_bo *bo;
switch(access) {
case GLAMOR_GPU_ACCESS_RW:
case GLAMOR_GPU_ACCESS_RO:
break;
case GLAMOR_CPU_ACCESS_RO:
case GLAMOR_CPU_ACCESS_RW:
bo = radeon_get_pixmap_bo(pixmap);
if (bo) {
radeon_bo_unmap(bo);
pixmap->devPrivate.ptr = NULL;
}
break;
default:
ErrorF("Invalid access mode %d\n", access);
}
return;
}
static PixmapPtr
radeon_glamor_create_pixmap(ScreenPtr screen, int w, int h, int depth,
unsigned usage)
{
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
RADEONInfoPtr info = RADEONPTR(scrn);
struct radeon_pixmap *priv;
PixmapPtr pixmap, new_pixmap = NULL;
if (!(usage & RADEON_CREATE_PIXMAP_DRI2)) {
pixmap = glamor_create_pixmap(screen, w, h, depth, usage);
if (pixmap)
return pixmap;
if (info->ChipFamily < CHIP_FAMILY_TAHITI) {
pixmap = glamor_create_pixmap(screen, w, h, depth, usage);
if (pixmap)
return pixmap;
} else
return fbCreatePixmap(screen, w, h, depth, usage);
}
if (w > 32767 || h > 32767)
@@ -230,9 +297,13 @@ Bool
radeon_glamor_init(ScreenPtr screen)
{
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
RADEONInfoPtr info = RADEONPTR(scrn);
unsigned int glamor_init_flags = GLAMOR_INVERTED_Y_AXIS | GLAMOR_USE_EGL_SCREEN;
if (!glamor_init(screen, GLAMOR_INVERTED_Y_AXIS | GLAMOR_USE_EGL_SCREEN |
GLAMOR_USE_SCREEN | GLAMOR_USE_PICTURE_SCREEN)) {
if (info->ChipFamily < CHIP_FAMILY_TAHITI)
glamor_init_flags |= GLAMOR_USE_SCREEN | GLAMOR_USE_PICTURE_SCREEN;
if (!glamor_init(screen, glamor_init_flags)) {
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
"Failed to initialize glamor.\n");
return FALSE;
@@ -251,6 +322,13 @@ radeon_glamor_init(ScreenPtr screen)
#endif
return FALSE;
if (!(glamor_init_flags & GLAMOR_USE_SCREEN) &&
!glamor_screen_init(screen)) {
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
"GLAMOR initialization failed\n");
return FALSE;
}
screen->CreatePixmap = radeon_glamor_create_pixmap;
screen->DestroyPixmap = radeon_glamor_destroy_pixmap;

5
src/radeon_glamor.h
View File

@@ -29,6 +29,7 @@
#ifdef USE_GLAMOR
#include "radeon_glamor_wrappers.h"
#include "radeon_surface.h"
Bool radeon_glamor_pre_init(ScrnInfoPtr scrn);
@@ -42,6 +43,8 @@ Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap);
void radeon_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst);
Bool radeon_glamor_pixmap_is_offscreen(PixmapPtr pixmap);
Bool radeon_glamor_prepare_access(PixmapPtr pixmap, glamor_access_t access);
void radeon_glamor_finish_access(PixmapPtr pixmap, glamor_access_t access);
struct radeon_pixmap {
struct radeon_surface surface;
@@ -85,6 +88,8 @@ static inline Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap) { retu
static inline void radeon_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst) {}
static inline Bool radeon_glamor_pixmap_is_offscreen(PixmapPtr pixmap) { return FALSE; }
static inline Bool radeon_glamor_prepare_access(PixmapPtr pixmap, int access) { return FALSE; }
static inline void radeon_glamor_finish_access(PixmapPtr pixmap, int access) {}
static inline struct radeon_pixmap *radeon_get_pixmap_private(PixmapPtr pixmap) { return NULL; }

1870
src/radeon_glamor_wrappers.c Normal file
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File diff suppressed because it is too large Load Diff

179
src/radeon_glamor_wrappers.h Normal file
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@@ -0,0 +1,179 @@
/*
* Copyright © 2000,2008 Keith Packard
* 2004 Eric Anholt
* 2005 Zack Rusin, Trolltech
* 2012 Advanced Micro Devices, Inc.
*
* Permission to use, copy, modify, distribute, and sell this software and its
* documentation for any purpose is hereby granted without fee, provided that
* the above copyright notice appear in all copies and that both that
* copyright notice and this permission notice appear in supporting
* documentation, and that the name of The copyright holders not be used in
* advertising or publicity pertaining to distribution of the software without
* specific, written prior permission. The copyright holders make no
* representations about the suitability of this software for any purpose. It
* is provided "as is" without express or implied warranty.
*
* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS
* SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS, IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY
* SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
* AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
* OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
* SOFTWARE.
*/
#ifndef RADEON_GLAMOR_WRAPPERS_H
#define RADEON_GLAMOR_WRAPPERS_H
#ifdef HAVE_CONFIG_H
#include <config.h>
#endif
#ifdef HAVE_DIX_CONFIG_H
#include <dix-config.h>
#endif
#include <xorg-server.h>
#include "xf86.h"
#include <X11/X.h>
#include <X11/Xproto.h>
#include "scrnintstr.h"
#include "pixmapstr.h"
#include "windowstr.h"
#include "servermd.h"
#include "mibstore.h"
#include "colormapst.h"
#include "gcstruct.h"
#include "input.h"
#include "mipointer.h"
#include "mi.h"
#include "dix.h"
#include "fb.h"
#include "fboverlay.h"
#ifdef RENDER
//#include "fbpict.h"
#include "glyphstr.h"
#include "picturestr.h"
#endif
#include "damage.h"
#include "../src/compat-api.h"
/* Provide substitutes for gcc's __FUNCTION__ on other compilers */
#if !defined(__GNUC__) && !defined(__FUNCTION__)
# if defined(__STDC__) && (__STDC_VERSION__>=199901L) /* C99 */
# define __FUNCTION__ __func__
# else
# define __FUNCTION__ ""
# endif
#endif
/* 1.6 and earlier server compat */
#ifndef miGetCompositeClip
#define miCopyRegion fbCopyRegion
#define miDoCopy fbDoCopy
#endif
typedef enum {
GLAMOR_CPU_ACCESS_RO,
GLAMOR_CPU_ACCESS_RW,
GLAMOR_GPU_ACCESS_RO,
GLAMOR_GPU_ACCESS_RW
} glamor_access_t;
#include "radeon.h"
#include "glamor.h"
Bool glamor_screen_init(ScreenPtr screen);
void glamor_set_fallback_debug(ScreenPtr screen, Bool enable);
#define DEBUG_MIGRATE 0
#define DEBUG_PIXMAP 0
#define DEBUG_OFFSCREEN 0
#define DEBUG_GLYPH_CACHE 0
#define GLAMOR_FALLBACK(x) \
if (glamor_get_screen(screen)->fallback_debug) { \
ErrorF("GLAMOR fallback at %s: ", __FUNCTION__); \
ErrorF x; \
}
#if DEBUG_PIXMAP
#define DBG_PIXMAP(a) ErrorF a
#else
#define DBG_PIXMAP(a)
#endif
typedef void (*EnableDisableFBAccessProcPtr) (int, Bool);
typedef struct {
CreateGCProcPtr SavedCreateGC;
CloseScreenProcPtr SavedCloseScreen;
GetImageProcPtr SavedGetImage;
GetSpansProcPtr SavedGetSpans;
CreatePixmapProcPtr SavedCreatePixmap;
DestroyPixmapProcPtr SavedDestroyPixmap;
CopyWindowProcPtr SavedCopyWindow;
ChangeWindowAttributesProcPtr SavedChangeWindowAttributes;
BitmapToRegionProcPtr SavedBitmapToRegion;
#ifdef RENDER
CompositeProcPtr SavedComposite;
TrianglesProcPtr SavedTriangles;
GlyphsProcPtr SavedGlyphs;
TrapezoidsProcPtr SavedTrapezoids;
AddTrapsProcPtr SavedAddTraps;
UnrealizeGlyphProcPtr SavedUnrealizeGlyph;
#endif
Bool fallback_debug;
} glamor_screen_t;
/*
* This is the only completely portable way to
* compute this info.
*/
#ifndef BitsPerPixel
#define BitsPerPixel(d) (\
PixmapWidthPaddingInfo[d].notPower2 ? \
(PixmapWidthPaddingInfo[d].bytesPerPixel * 8) : \
((1 << PixmapWidthPaddingInfo[d].padBytesLog2) * 8 / \
(PixmapWidthPaddingInfo[d].padRoundUp+1)))
#endif
#if HAS_DEVPRIVATEKEYREC
extern DevPrivateKeyRec glamor_screen_index;
#else
extern int glamor_screen_index;
#endif
static inline glamor_screen_t *glamor_get_screen(ScreenPtr screen)
{
#if HAS_DEVPRIVATEKEYREC
return dixGetPrivate(&screen->devPrivates, &glamor_screen_index);
#else
return dixLookupPrivate(&screen->devPrivates, &glamor_screen_index);
#endif
}
#ifdef RENDER
/* XXX these are in fbpict.h, which is not installed */
void
fbComposite(CARD8 op,
PicturePtr pSrc,
PicturePtr pMask,
PicturePtr pDst,
INT16 xSrc,
INT16 ySrc,
INT16 xMask,
INT16 yMask, INT16 xDst, INT16 yDst, CARD16 width, CARD16 height);
void
fbAddTraps(PicturePtr pPicture,
INT16 xOff, INT16 yOff, int ntrap, xTrap * traps);
#endif
#endif /* RADEON_GLAMOR_WRAPPERS_H */

5
src/radeon_kms.c
View File

@@ -418,6 +418,7 @@ static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
(!RADEONIsAccelWorking(pScrn))) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"GPU accel disabled or not working, using shadowfb for KMS\n");
shadowfb:
info->r600_shadow_fb = TRUE;
if (!xf86LoadSubModule(pScrn, "shadow"))
info->r600_shadow_fb = FALSE;
@@ -427,7 +428,9 @@ static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
if (radeon_glamor_pre_init(pScrn))
return TRUE;
if (info->ChipFamily == CHIP_FAMILY_PALM) {
if (info->ChipFamily >= CHIP_FAMILY_TAHITI) {
goto shadowfb;
} else if (info->ChipFamily == CHIP_FAMILY_PALM) {
info->accel_state->allowHWDFS = RADEONIsFusionGARTWorking(pScrn);
} else
info->accel_state->allowHWDFS = TRUE;

39
src/radeon_pci_chipset_gen.h
View File

@@ -537,5 +537,44 @@ static PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_ARUBA_99A0, PCI_CHIP_ARUBA_99A0, RES_SHARED_VGA },
{ PCI_CHIP_ARUBA_99A2, PCI_CHIP_ARUBA_99A2, RES_SHARED_VGA },
{ PCI_CHIP_ARUBA_99A4, PCI_CHIP_ARUBA_99A4, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_6780, PCI_CHIP_TAHITI_6780, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_6784, PCI_CHIP_TAHITI_6784, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_6788, PCI_CHIP_TAHITI_6788, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_678A, PCI_CHIP_TAHITI_678A, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_6790, PCI_CHIP_TAHITI_6790, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_6798, PCI_CHIP_TAHITI_6798, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_6799, PCI_CHIP_TAHITI_6799, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_679A, PCI_CHIP_TAHITI_679A, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_679E, PCI_CHIP_TAHITI_679E, RES_SHARED_VGA },
{ PCI_CHIP_TAHITI_679F, PCI_CHIP_TAHITI_679F, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6800, PCI_CHIP_PITCAIRN_6800, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6801, PCI_CHIP_PITCAIRN_6801, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6802, PCI_CHIP_PITCAIRN_6802, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6808, PCI_CHIP_PITCAIRN_6808, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6809, PCI_CHIP_PITCAIRN_6809, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6810, PCI_CHIP_PITCAIRN_6810, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6818, PCI_CHIP_PITCAIRN_6818, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_6819, PCI_CHIP_PITCAIRN_6819, RES_SHARED_VGA },
{ PCI_CHIP_PITCAIRN_684C, PCI_CHIP_PITCAIRN_684C, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6820, PCI_CHIP_VERDE_6820, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6821, PCI_CHIP_VERDE_6821, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6823, PCI_CHIP_VERDE_6823, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6824, PCI_CHIP_VERDE_6824, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6825, PCI_CHIP_VERDE_6825, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6826, PCI_CHIP_VERDE_6826, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6827, PCI_CHIP_VERDE_6827, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6828, PCI_CHIP_VERDE_6828, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6829, PCI_CHIP_VERDE_6829, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_682B, PCI_CHIP_VERDE_682B, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_682D, PCI_CHIP_VERDE_682D, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_682F, PCI_CHIP_VERDE_682F, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6830, PCI_CHIP_VERDE_6830, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6831, PCI_CHIP_VERDE_6831, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6837, PCI_CHIP_VERDE_6837, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6838, PCI_CHIP_VERDE_6838, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_6839, PCI_CHIP_VERDE_6839, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_683B, PCI_CHIP_VERDE_683B, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_683D, PCI_CHIP_VERDE_683D, RES_SHARED_VGA },
{ PCI_CHIP_VERDE_683F, PCI_CHIP_VERDE_683F, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};

39
src/radeon_pci_device_match_gen.h
View File

@@ -537,5 +537,44 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_99A0, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_99A2, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_99A4, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6780, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6784, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6788, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_678A, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6790, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6798, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6799, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679A, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679E, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6800, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6801, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6802, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6808, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6809, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6810, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6818, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6819, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_684C, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6820, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6821, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6823, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6824, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6825, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6826, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6827, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6828, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6829, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682D, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6830, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6831, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6837, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6838, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6839, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683D, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683F, 0 ),
{ 0, 0, 0 }
};

3
src/radeon_probe.h
View File

@@ -102,6 +102,9 @@ typedef enum {
CHIP_FAMILY_CAICOS,
CHIP_FAMILY_CAYMAN,
CHIP_FAMILY_ARUBA,
CHIP_FAMILY_TAHITI,
CHIP_FAMILY_PITCAIRN,
CHIP_FAMILY_VERDE,
CHIP_FAMILY_LAST
} RADEONChipFamily;

1
src/radeon_version.h
View File

@@ -39,6 +39,7 @@
#define R200_DRIVER_NAME "r200"
#define R300_DRIVER_NAME "r300"
#define R600_DRIVER_NAME "r600"
#define SI_DRIVER_NAME "radeonsi"
#define RADEON_VERSION_MAJOR PACKAGE_VERSION_MAJOR
#define RADEON_VERSION_MINOR PACKAGE_VERSION_MINOR