mirror of
https://github.com/X11Libre/xf86-video-ati.git
synced 2026-03-24 01:24:43 +00:00
Add file missed in last commit: Bug #748:
- Add Render acceleration for Radeon 100 and 200-series cards, enabled by
default. Notable performance gains include 27fps in cairogears instead
of 6fps (compared to 50 with glitz), and my disks are now the
bottleneck in an ls -lR in gnome-terminal. Only supported in DRI mode
because the MMIO submission hangs the card so far, but the code is left
in because it may be supportable soon.
- Add xorg.conf options to disable Render acceleration and to force the
subpixel order in the server (Hui Yu).
Many thanks to Hui Yu at ATI for the code this was based off of, Michel
Daenzer for bugfixes and suggestions, and LinuxFund for sponsoring the
work.
This commit is contained in:
Eric Anholt
854
src/radeon_render.c
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854
src/radeon_render.c
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@@ -0,0 +1,854 @@
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#include "dixstruct.h"
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#include "xaa.h"
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#include "xaalocal.h"
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#ifndef RENDER_GENERIC_HELPER
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#define RENDER_GENERIC_HELPER
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static void RadeonInit3DEngineMMIO(ScrnInfoPtr pScrn);
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#ifdef XF86DRI
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static void RadeonInit3DEngineCP(ScrnInfoPtr pScrn);
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#endif
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struct blendinfo {
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Bool dst_alpha;
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Bool src_alpha;
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CARD32 blend_cntl;
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};
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/* The first part of blend_cntl corresponds to Fa from the render "protocol"
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* document, and the second part to Fb.
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*/
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static const struct blendinfo RadeonBlendOp[] = {
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/* Clear */
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{0, 0, RADEON_SRC_BLEND_GL_ZERO |
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RADEON_DST_BLEND_GL_ZERO},
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/* Src */
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{0, 0, RADEON_SRC_BLEND_GL_ONE |
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RADEON_DST_BLEND_GL_ZERO},
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/* Dst */
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{0, 0, RADEON_SRC_BLEND_GL_ZERO |
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RADEON_DST_BLEND_GL_ONE},
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/* Over */
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{0, 1, RADEON_SRC_BLEND_GL_ONE |
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RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
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/* OverReverse */
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{1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA |
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RADEON_DST_BLEND_GL_ONE},
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/* In */
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{1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA |
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RADEON_DST_BLEND_GL_ZERO},
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/* InReverse */
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{0, 1, RADEON_SRC_BLEND_GL_ZERO |
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RADEON_DST_BLEND_GL_SRC_ALPHA},
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/* Out */
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{1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA |
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RADEON_DST_BLEND_GL_ZERO},
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/* OutReverse */
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{0, 1, RADEON_SRC_BLEND_GL_ZERO |
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RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
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/* Atop */
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{1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA |
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RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
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/* AtopReverse */
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{1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA |
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RADEON_DST_BLEND_GL_SRC_ALPHA},
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/* Xor */
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{1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA |
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RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
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/* Add */
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{0, 0, RADEON_SRC_BLEND_GL_ONE |
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RADEON_DST_BLEND_GL_ONE},
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/* Saturate */
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{0, 1, RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE |
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RADEON_DST_BLEND_GL_ONE},
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{0, 0, 0},
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{0, 0, 0},
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/* DisjointClear */
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{0, 0, RADEON_SRC_BLEND_GL_ZERO |
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RADEON_DST_BLEND_GL_ZERO},
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/* DisjointSrc */
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{0, 0, RADEON_SRC_BLEND_GL_ONE |
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RADEON_DST_BLEND_GL_ZERO},
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/* DisjointDst */
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{0, 0, RADEON_SRC_BLEND_GL_ZERO |
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RADEON_DST_BLEND_GL_ONE},
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/* DisjointOver unsupported */
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{0, 0, 0},
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/* DisjointOverReverse */
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{1, 1, RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE |
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RADEON_DST_BLEND_GL_ONE},
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/* DisjointIn unsupported */
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{0, 0, 0},
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/* DisjointInReverse unsupported */
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{0, 0, 0},
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/* DisjointOut unsupported */
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{1, 1, RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE |
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RADEON_DST_BLEND_GL_ZERO},
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/* DisjointOutReverse unsupported */
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{0, 0, 0},
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/* DisjointAtop unsupported */
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{0, 0, 0},
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/* DisjointAtopReverse unsupported */
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{0, 0, 0},
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/* DisjointXor unsupported */
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{0, 0, 0},
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{0, 0, 0},
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{0, 0, 0},
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{0, 0, 0},
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{0, 0, 0},
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/* ConjointClear */
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{0, 0, RADEON_SRC_BLEND_GL_ZERO |
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RADEON_DST_BLEND_GL_ZERO},
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/* ConjointSrc */
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{0, 0, RADEON_SRC_BLEND_GL_ONE |
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RADEON_DST_BLEND_GL_ZERO},
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/* ConjointDst */
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{0, 0, RADEON_SRC_BLEND_GL_ZERO |
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RADEON_DST_BLEND_GL_ONE},
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};
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#define RadeonOpMax (sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0]))
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/* Note on texture formats:
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* TXFORMAT_Y8 expands to (Y,Y,Y,1). TXFORMAT_I8 expands to (I,I,I,I)
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* The RADEON and R200 TXFORMATS we use are the same on r100/r200.
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*/
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static CARD32 RADEONTextureFormats[] = {
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PICT_a8r8g8b8,
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PICT_a8,
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PICT_x8r8g8b8,
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PICT_r5g6b5,
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PICT_x1r5g5b5,
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};
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static void RadeonGetTextureFormat(CARD32 format, CARD32 *txformat, int *bytepp)
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{
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switch (format) {
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case PICT_a8r8g8b8:
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*txformat = RADEON_TXFORMAT_ARGB8888 | RADEON_TXFORMAT_ALPHA_IN_MAP;
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*bytepp = 4;
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break;
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case PICT_a8:
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*txformat = RADEON_TXFORMAT_I8 | RADEON_TXFORMAT_ALPHA_IN_MAP;
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*bytepp = 1;
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break;
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case PICT_x8r8g8b8:
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*txformat = RADEON_TXFORMAT_ARGB8888;
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*bytepp = 4;
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break;
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case PICT_r5g6b5:
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*txformat = RADEON_TXFORMAT_RGB565;
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*bytepp = 2;
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break;
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case PICT_a1r5g5b5:
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*txformat = RADEON_TXFORMAT_ARGB1555 | RADEON_TXFORMAT_ALPHA_IN_MAP;
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*bytepp = 2;
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break;
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case PICT_x1r5g5b5:
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*txformat = RADEON_TXFORMAT_ARGB1555;
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*bytepp = 2;
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break;
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}
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}
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static __inline__ CARD32 F_TO_DW(float val)
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{
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union {
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float f;
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CARD32 l;
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} tmp;
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tmp.f = val;
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return tmp.l;
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}
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/* Compute log base 2 of val. */
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static __inline__ int
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ATILog2(int val)
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{
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int bits;
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for (bits = 0; val != 0; val >>= 1, ++bits)
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;
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return bits - 1;
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}
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void RADEONInit3DEngineForRender(ScrnInfoPtr pScrn)
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{
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RADEONInfoPtr info = RADEONPTR (pScrn);
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#ifdef XF86DRI
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if (info->directRenderingEnabled)
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RadeonInit3DEngineCP(pScrn);
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else
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#endif
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RadeonInit3DEngineMMIO(pScrn);
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}
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static void
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RemoveLinear (FBLinearPtr linear)
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{
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RADEONInfoPtr info = (RADEONInfoPtr)(linear->devPrivate.ptr);
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info->RenderTex = NULL;
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}
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static void
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RenderCallback (ScrnInfoPtr pScrn)
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{
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RADEONInfoPtr info = RADEONPTR(pScrn);
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if ((currentTime.milliseconds > info->RenderTimeout) && info->RenderTex) {
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xf86FreeOffscreenLinear(info->RenderTex);
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info->RenderTex = NULL;
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}
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if (!info->RenderTex)
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info->RenderCallback = NULL;
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}
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static Bool
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AllocateLinear (
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ScrnInfoPtr pScrn,
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int sizeNeeded
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){
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RADEONInfoPtr info = RADEONPTR(pScrn);
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info->RenderTimeout = currentTime.milliseconds + 30000;
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info->RenderCallback = RenderCallback;
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if (info->RenderTex) {
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if (info->RenderTex->size >= sizeNeeded)
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return TRUE;
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else {
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if (xf86ResizeOffscreenLinear(info->RenderTex, sizeNeeded))
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return TRUE;
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xf86FreeOffscreenLinear(info->RenderTex);
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info->RenderTex = NULL;
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}
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}
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info->RenderTex = xf86AllocateOffscreenLinear(pScrn->pScreen, sizeNeeded, 32,
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NULL, RemoveLinear, info);
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return (info->RenderTex != NULL);
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}
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#endif
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#if defined(ACCEL_MMIO) && defined(ACCEL_CP)
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#error Cannot define both MMIO and CP acceleration!
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#endif
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#if !defined(UNIXCPP) || defined(ANSICPP)
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#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
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#else
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#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
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#endif
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#ifdef ACCEL_MMIO
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#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO)
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#else
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#ifdef ACCEL_CP
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#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
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#else
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#error No accel type defined!
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#endif
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#endif
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static void FUNC_NAME(RadeonInit3DEngine)(ScrnInfoPtr pScrn)
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{
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RADEONInfoPtr info = RADEONPTR(pScrn);
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ACCEL_PREAMBLE();
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if (info->ChipFamily >= CHIP_FAMILY_R300) {
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/* Unimplemented */
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} else if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
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(info->ChipFamily == CHIP_FAMILY_RV280) ||
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(info->ChipFamily == CHIP_FAMILY_RS300) ||
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(info->ChipFamily == CHIP_FAMILY_R200)) {
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BEGIN_ACCEL(7);
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OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0);
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OUT_ACCEL_REG(R200_PP_CNTL_X, 0);
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OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0);
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OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0);
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OUT_ACCEL_REG(R200_RE_CNTL, 0x0);
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/* XXX: correct? Want it to be like RADEON_VTX_ST?_NONPARAMETRIC */
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OUT_ACCEL_REG(R200_SE_VTE_CNTL, R200_VTX_ST_DENORMALIZED);
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OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE |
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R200_VAP_VF_MAX_VTX_NUM);
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FINISH_ACCEL();
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} else {
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BEGIN_ACCEL(2);
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OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
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OUT_ACCEL_REG(RADEON_SE_COORD_FMT,
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RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
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RADEON_VTX_ST0_NONPARAMETRIC |
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RADEON_VTX_ST1_NONPARAMETRIC |
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RADEON_TEX1_W_ROUTING_USE_W0);
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FINISH_ACCEL();
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}
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BEGIN_ACCEL(3);
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OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
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OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
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OUT_ACCEL_REG(RADEON_SE_CNTL, RADEON_DIFFUSE_SHADE_GOURAUD |
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RADEON_BFACE_SOLID |
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RADEON_FFACE_SOLID |
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RADEON_VTX_PIX_CENTER_OGL |
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RADEON_ROUND_MODE_ROUND |
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RADEON_ROUND_PREC_4TH_PIX);
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FINISH_ACCEL();
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}
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static Bool FUNC_NAME(R100SetupTexture)(ScrnInfoPtr pScrn,
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int format,
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CARD8 *src,
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int src_pitch,
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int width,
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int height,
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int flags)
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{
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RADEONInfoPtr info = RADEONPTR(pScrn);
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CARD8 *dst;
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CARD32 tex_size = 0, txformat;
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int dst_pitch, offset, size, i, tex_bytepp;
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ACCEL_PREAMBLE();
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if ((width > 2048) || (height > 2048))
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return FALSE;
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RadeonGetTextureFormat(format, &txformat, &tex_bytepp);
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dst_pitch = (width * tex_bytepp + 31) & ~31;
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size = dst_pitch * height;
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if (!AllocateLinear(pScrn, size))
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return FALSE;
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if (flags & XAA_RENDER_REPEAT) {
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txformat |= ATILog2(width) << RADEON_TXFORMAT_WIDTH_SHIFT;
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txformat |= ATILog2(height) << RADEON_TXFORMAT_HEIGHT_SHIFT;
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} else {
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tex_size = ((height - 1) << 16) | (width - 1);
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txformat |= RADEON_TXFORMAT_NON_POWER2;
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}
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offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8;
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/* Upload texture to card. Should use ImageWrite to avoid syncing. */
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i = height;
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dst = (CARD8*)(info->FB + offset);
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if (info->accel->NeedToSync)
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info->accel->Sync(pScrn);
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while(i--) {
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memcpy(dst, src, width * tex_bytepp);
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src += src_pitch;
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dst += dst_pitch;
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}
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BEGIN_ACCEL(5);
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OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat);
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OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0, tex_size);
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OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_0, dst_pitch - 32);
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OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, offset + info->fbLocation +
|
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pScrn->fbOffset);
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OUT_ACCEL_REG(RADEON_PP_TXFILTER_0, RADEON_MAG_FILTER_LINEAR |
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RADEON_MIN_FILTER_LINEAR |
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RADEON_CLAMP_S_WRAP |
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RADEON_CLAMP_T_WRAP);
|
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FINISH_ACCEL();
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return TRUE;
|
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}
|
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static Bool
|
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FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) (
|
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ScrnInfoPtr pScrn,
|
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int op,
|
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CARD16 red,
|
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CARD16 green,
|
||||
CARD16 blue,
|
||||
CARD16 alpha,
|
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int alphaFormat,
|
||||
CARD8 *alphaPtr,
|
||||
int alphaPitch,
|
||||
int width,
|
||||
int height,
|
||||
int flags
|
||||
)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
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CARD32 format, srccolor;
|
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ACCEL_PREAMBLE();
|
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if (op >= RadeonOpMax || RadeonBlendOp[op].blend_cntl == 0)
|
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return FALSE;
|
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|
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if (!FUNC_NAME(R100SetupTexture)(pScrn, alphaFormat, alphaPtr, alphaPitch,
|
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width, height, flags))
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return FALSE;
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if (pScrn->bitsPerPixel == 32)
|
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format = RADEON_COLOR_FORMAT_ARGB8888;
|
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else
|
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format = RADEON_COLOR_FORMAT_RGB565;
|
||||
|
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srccolor = ((alpha & 0xff00) << 16) | ((red & 0xff00) << 8) | (blue >> 8) |
|
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(green & 0xff00);
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BEGIN_ACCEL(8);
|
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OUT_ACCEL_REG(RADEON_RB3D_CNTL, format | RADEON_ALPHA_BLEND_ENABLE);
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OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth);
|
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OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
|
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RADEON_TEX_BLEND_0_ENABLE);
|
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OUT_ACCEL_REG(RADEON_PP_TFACTOR_0, srccolor);
|
||||
OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_A_TFACTOR_COLOR |
|
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RADEON_COLOR_ARG_B_T0_ALPHA);
|
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OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, RADEON_ALPHA_ARG_A_TFACTOR_ALPHA |
|
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RADEON_ALPHA_ARG_B_T0_ALPHA);
|
||||
OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY |
|
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RADEON_SE_VTX_FMT_ST0);
|
||||
OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL,
|
||||
RadeonBlendOp[op].blend_cntl);
|
||||
FINISH_ACCEL();
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
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static Bool
|
||||
FUNC_NAME(R100SetupForCPUToScreenTexture) (
|
||||
ScrnInfoPtr pScrn,
|
||||
int op,
|
||||
int texFormat,
|
||||
CARD8 *texPtr,
|
||||
int texPitch,
|
||||
int width,
|
||||
int height,
|
||||
int flags
|
||||
)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
CARD32 format;
|
||||
ACCEL_PREAMBLE();
|
||||
|
||||
if (op >= RadeonOpMax || RadeonBlendOp[op].blend_cntl == 0)
|
||||
return FALSE;
|
||||
|
||||
if (!FUNC_NAME(R100SetupTexture)(pScrn, texFormat, texPtr, texPitch, width,
|
||||
height, flags))
|
||||
return FALSE;
|
||||
|
||||
if (pScrn->bitsPerPixel == 32)
|
||||
format = RADEON_COLOR_FORMAT_ARGB8888;
|
||||
else
|
||||
format = RADEON_COLOR_FORMAT_RGB565;
|
||||
|
||||
BEGIN_ACCEL(7);
|
||||
OUT_ACCEL_REG(RADEON_RB3D_CNTL, format | RADEON_ALPHA_BLEND_ENABLE);
|
||||
OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth);
|
||||
OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
|
||||
RADEON_TEX_BLEND_0_ENABLE);
|
||||
if (texFormat != PICT_a8)
|
||||
OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_C_T0_COLOR);
|
||||
else
|
||||
OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_C_ZERO);
|
||||
OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, RADEON_ALPHA_ARG_C_T0_ALPHA);
|
||||
OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY |
|
||||
RADEON_SE_VTX_FMT_ST0);
|
||||
OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL,
|
||||
RadeonBlendOp[op].blend_cntl);
|
||||
FINISH_ACCEL();
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
FUNC_NAME(R100SubsequentCPUToScreenTexture) (
|
||||
ScrnInfoPtr pScrn,
|
||||
int dstx,
|
||||
int dsty,
|
||||
int srcx,
|
||||
int srcy,
|
||||
int width,
|
||||
int height
|
||||
)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
int byteshift;
|
||||
CARD32 fboffset;
|
||||
float l, t, r, b, fl, fr, ft, fb;
|
||||
|
||||
ACCEL_PREAMBLE();
|
||||
|
||||
/* Note: we can't simply set up the 3D surface at the same location as the
|
||||
* front buffer, because the 2048x2048 limit on coordinates may be smaller
|
||||
* than the (MergedFB) screen.
|
||||
*/
|
||||
byteshift = (pScrn->bitsPerPixel >> 4);
|
||||
fboffset = (info->fbLocation + pScrn->fbOffset +
|
||||
((pScrn->displayWidth * dsty + dstx) << byteshift)) & ~15;
|
||||
l = ((dstx << byteshift) % 16) >> byteshift;
|
||||
t = 0.0;
|
||||
r = width + l;
|
||||
b = height;
|
||||
fl = srcx;
|
||||
fr = srcx + width;
|
||||
ft = srcy;
|
||||
fb = srcy + height;
|
||||
|
||||
#ifdef ACCEL_CP
|
||||
BEGIN_RING(23);
|
||||
|
||||
OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset);
|
||||
|
||||
OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, 17));
|
||||
/* RADEON_SE_VTX_FMT */
|
||||
OUT_RING(RADEON_CP_VC_FRMT_XY |
|
||||
RADEON_CP_VC_FRMT_ST0);
|
||||
/* SE_VF_CNTL */
|
||||
OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
|
||||
RADEON_CP_VC_CNTL_PRIM_WALK_RING |
|
||||
RADEON_CP_VC_CNTL_MAOS_ENABLE |
|
||||
RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
|
||||
(4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
|
||||
|
||||
OUT_RING(F_TO_DW(l));
|
||||
OUT_RING(F_TO_DW(t));
|
||||
OUT_RING(F_TO_DW(fl));
|
||||
OUT_RING(F_TO_DW(ft));
|
||||
|
||||
OUT_RING(F_TO_DW(r));
|
||||
OUT_RING(F_TO_DW(t));
|
||||
OUT_RING(F_TO_DW(fr));
|
||||
OUT_RING(F_TO_DW(ft));
|
||||
|
||||
OUT_RING(F_TO_DW(r));
|
||||
OUT_RING(F_TO_DW(b));
|
||||
OUT_RING(F_TO_DW(fr));
|
||||
OUT_RING(F_TO_DW(fb));
|
||||
|
||||
OUT_RING(F_TO_DW(l));
|
||||
OUT_RING(F_TO_DW(b));
|
||||
OUT_RING(F_TO_DW(fl));
|
||||
OUT_RING(F_TO_DW(fb));
|
||||
|
||||
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
|
||||
|
||||
ADVANCE_RING();
|
||||
#else
|
||||
BEGIN_ACCEL(19);
|
||||
|
||||
OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset);
|
||||
|
||||
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, RADEON_VF_PRIM_TYPE_TRIANGLE_FAN |
|
||||
RADEON_VF_PRIM_WALK_DATA |
|
||||
RADEON_VF_RADEON_MODE |
|
||||
(4 << RADEON_VF_NUM_VERTICES_SHIFT));
|
||||
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft));
|
||||
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft));
|
||||
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb));
|
||||
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb));
|
||||
|
||||
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
|
||||
FINISH_ACCEL();
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
static Bool FUNC_NAME(R200SetupTexture)(ScrnInfoPtr pScrn,
|
||||
int format,
|
||||
CARD8 *src,
|
||||
int src_pitch,
|
||||
int width,
|
||||
int height,
|
||||
int flags)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
CARD8 *dst;
|
||||
CARD32 tex_size = 0, txformat;
|
||||
int dst_pitch, offset, size, i, tex_bytepp;
|
||||
ACCEL_PREAMBLE();
|
||||
|
||||
if ((width > 2048) || (height > 2048))
|
||||
return FALSE;
|
||||
|
||||
RadeonGetTextureFormat(format, &txformat, &tex_bytepp);
|
||||
|
||||
dst_pitch = (width * tex_bytepp + 31) & ~31;
|
||||
size = dst_pitch * height;
|
||||
|
||||
if (!AllocateLinear(pScrn, size))
|
||||
return FALSE;
|
||||
|
||||
if (flags & XAA_RENDER_REPEAT) {
|
||||
txformat |= ATILog2(width) << R200_TXFORMAT_WIDTH_SHIFT;
|
||||
txformat |= ATILog2(height) << R200_TXFORMAT_HEIGHT_SHIFT;
|
||||
} else {
|
||||
tex_size = ((height - 1) << 16) | (width - 1);
|
||||
txformat |= RADEON_TXFORMAT_NON_POWER2;
|
||||
}
|
||||
|
||||
offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8;
|
||||
|
||||
/* Upload texture to card. Should use ImageWrite to avoid syncing. */
|
||||
i = height;
|
||||
dst = (CARD8*)(info->FB + offset);
|
||||
if (info->accel->NeedToSync)
|
||||
info->accel->Sync(pScrn);
|
||||
while(i--) {
|
||||
memcpy(dst, src, width * tex_bytepp);
|
||||
src += src_pitch;
|
||||
dst += dst_pitch;
|
||||
}
|
||||
|
||||
BEGIN_ACCEL(6);
|
||||
OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat);
|
||||
OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0);
|
||||
OUT_ACCEL_REG(R200_PP_TXSIZE_0, tex_size);
|
||||
OUT_ACCEL_REG(R200_PP_TXPITCH_0, dst_pitch - 32);
|
||||
OUT_ACCEL_REG(R200_PP_TXOFFSET_0, offset + info->fbLocation +
|
||||
pScrn->fbOffset);
|
||||
OUT_ACCEL_REG(R200_PP_TXFILTER_0, R200_MAG_FILTER_NEAREST |
|
||||
R200_MIN_FILTER_NEAREST |
|
||||
R200_CLAMP_S_WRAP |
|
||||
R200_CLAMP_T_WRAP);
|
||||
FINISH_ACCEL();
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static Bool
|
||||
FUNC_NAME(R200SetupForCPUToScreenAlphaTexture) (
|
||||
ScrnInfoPtr pScrn,
|
||||
int op,
|
||||
CARD16 red,
|
||||
CARD16 green,
|
||||
CARD16 blue,
|
||||
CARD16 alpha,
|
||||
int alphaFormat,
|
||||
CARD8 *alphaPtr,
|
||||
int alphaPitch,
|
||||
int width,
|
||||
int height,
|
||||
int flags
|
||||
)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
CARD32 format, srccolor;
|
||||
ACCEL_PREAMBLE();
|
||||
|
||||
if (op >= RadeonOpMax || RadeonBlendOp[op].blend_cntl == 0)
|
||||
return FALSE;
|
||||
|
||||
if (!FUNC_NAME(R200SetupTexture)(pScrn, alphaFormat, alphaPtr, alphaPitch,
|
||||
width, height, flags))
|
||||
return FALSE;
|
||||
|
||||
if (pScrn->bitsPerPixel == 32)
|
||||
format = RADEON_COLOR_FORMAT_ARGB8888;
|
||||
else
|
||||
format = RADEON_COLOR_FORMAT_RGB565;
|
||||
|
||||
srccolor = ((alpha & 0xff00) << 16) | ((red & 0xff00) << 8) | (blue >> 8) |
|
||||
(green & 0xff00);
|
||||
|
||||
BEGIN_ACCEL(11);
|
||||
OUT_ACCEL_REG(RADEON_RB3D_CNTL, format | RADEON_ALPHA_BLEND_ENABLE);
|
||||
OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth);
|
||||
OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
|
||||
RADEON_TEX_BLEND_0_ENABLE);
|
||||
OUT_ACCEL_REG(R200_PP_TFACTOR_0, srccolor);
|
||||
OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_A_TFACTOR_COLOR |
|
||||
R200_TXC_ARG_B_R0_ALPHA);
|
||||
OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, R200_TXC_OUTPUT_REG_R0);
|
||||
OUT_ACCEL_REG(R200_PP_TXABLEND_0, R200_TXA_ARG_A_TFACTOR_ALPHA |
|
||||
R200_TXA_ARG_B_R0_ALPHA);
|
||||
OUT_ACCEL_REG(R200_PP_TXABLEND2_0, R200_TXA_OUTPUT_REG_R0);
|
||||
OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0);
|
||||
OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
|
||||
OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL,
|
||||
RadeonBlendOp[op].blend_cntl);
|
||||
FINISH_ACCEL();
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static Bool
|
||||
FUNC_NAME(R200SetupForCPUToScreenTexture) (
|
||||
ScrnInfoPtr pScrn,
|
||||
int op,
|
||||
int texFormat,
|
||||
CARD8 *texPtr,
|
||||
int texPitch,
|
||||
int width,
|
||||
int height,
|
||||
int flags
|
||||
)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
CARD32 format;
|
||||
ACCEL_PREAMBLE();
|
||||
|
||||
if (op >= RadeonOpMax || RadeonBlendOp[op].blend_cntl == 0)
|
||||
return FALSE;
|
||||
|
||||
if (!FUNC_NAME(R200SetupTexture)(pScrn, texFormat, texPtr, texPitch, width,
|
||||
height, flags))
|
||||
return FALSE;
|
||||
|
||||
if (pScrn->bitsPerPixel == 32)
|
||||
format = RADEON_COLOR_FORMAT_ARGB8888;
|
||||
else
|
||||
format = RADEON_COLOR_FORMAT_RGB565;
|
||||
|
||||
BEGIN_ACCEL(10);
|
||||
OUT_ACCEL_REG(RADEON_RB3D_CNTL, format | RADEON_ALPHA_BLEND_ENABLE);
|
||||
OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth);
|
||||
OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
|
||||
RADEON_TEX_BLEND_0_ENABLE);
|
||||
if (texFormat != PICT_a8)
|
||||
OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_C_R0_COLOR);
|
||||
else
|
||||
OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_C_ZERO);
|
||||
OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, R200_TXC_OUTPUT_REG_R0);
|
||||
OUT_ACCEL_REG(R200_PP_TXABLEND_0, R200_TXA_ARG_C_R0_ALPHA);
|
||||
OUT_ACCEL_REG(R200_PP_TXABLEND2_0, R200_TXA_OUTPUT_REG_R0);
|
||||
OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0);
|
||||
OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
|
||||
OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL,
|
||||
RadeonBlendOp[op].blend_cntl);
|
||||
FINISH_ACCEL();
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static void
|
||||
FUNC_NAME(R200SubsequentCPUToScreenTexture) (
|
||||
ScrnInfoPtr pScrn,
|
||||
int dstx,
|
||||
int dsty,
|
||||
int srcx,
|
||||
int srcy,
|
||||
int width,
|
||||
int height
|
||||
)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
int byteshift;
|
||||
CARD32 fboffset;
|
||||
float l, t, r, b, fl, fr, ft, fb;
|
||||
ACCEL_PREAMBLE();
|
||||
|
||||
/* Note: we can't simply set up the 3D surface at the same location as the
|
||||
* front buffer, because the 2048x2048 limit on coordinates may be smaller
|
||||
* than the (MergedFB) screen.
|
||||
*/
|
||||
byteshift = (pScrn->bitsPerPixel >> 4);
|
||||
fboffset = (info->fbLocation + pScrn->fbOffset + ((pScrn->displayWidth *
|
||||
dsty + dstx) << byteshift)) & ~15;
|
||||
l = ((dstx << byteshift) % 16) >> byteshift;
|
||||
t = 0.0;
|
||||
r = width + l;
|
||||
b = height;
|
||||
fl = srcx;
|
||||
fr = srcx + width;
|
||||
ft = srcy;
|
||||
fb = srcy + height;
|
||||
|
||||
#ifdef ACCEL_CP
|
||||
BEGIN_RING(24);
|
||||
|
||||
OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset);
|
||||
|
||||
OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, 16));
|
||||
/* RADEON_SE_VF_CNTL */
|
||||
OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
|
||||
RADEON_CP_VC_CNTL_PRIM_WALK_RING |
|
||||
(4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
|
||||
|
||||
OUT_RING(F_TO_DW(l));
|
||||
OUT_RING(F_TO_DW(t));
|
||||
OUT_RING(F_TO_DW(fl));
|
||||
OUT_RING(F_TO_DW(ft));
|
||||
|
||||
OUT_RING(F_TO_DW(r));
|
||||
OUT_RING(F_TO_DW(t));
|
||||
OUT_RING(F_TO_DW(fr));
|
||||
OUT_RING(F_TO_DW(ft));
|
||||
|
||||
OUT_RING(F_TO_DW(r));
|
||||
OUT_RING(F_TO_DW(b));
|
||||
OUT_RING(F_TO_DW(fr));
|
||||
OUT_RING(F_TO_DW(fb));
|
||||
|
||||
OUT_RING(F_TO_DW(l));
|
||||
OUT_RING(F_TO_DW(b));
|
||||
OUT_RING(F_TO_DW(fl));
|
||||
OUT_RING(F_TO_DW(fb));
|
||||
|
||||
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
|
||||
|
||||
ADVANCE_RING();
|
||||
#else
|
||||
BEGIN_ACCEL(19);
|
||||
|
||||
/* Note: we can't simply setup 3D surface at the same location as the front buffer,
|
||||
some apps may draw offscreen pictures out of the limitation of radeon 3D surface.
|
||||
*/
|
||||
OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset);
|
||||
|
||||
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST |
|
||||
RADEON_VF_PRIM_WALK_DATA |
|
||||
4 << RADEON_VF_NUM_VERTICES_SHIFT));
|
||||
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft));
|
||||
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft));
|
||||
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb));
|
||||
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl));
|
||||
OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb));
|
||||
|
||||
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
|
||||
|
||||
FINISH_ACCEL();
|
||||
#endif
|
||||
}
|
||||
|
||||
#undef FUNC_NAME
|
||||
|
||||
Reference in New Issue
Block a user